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Reduce verbosity

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This commit is contained in:
Akash Levy 2024-09-05 00:56:01 -07:00
parent 42dc3f6da6
commit bebdb2f035
2 changed files with 7 additions and 7 deletions
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6
passes/cmds/splitfanout.cc
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@ -80,7 +80,7 @@ struct SplitfanoutWorker
outsig = conn.second; outsig = conn.second;
} }
if (output_count != 1) { if (output_count != 1) {
log("Skipping %s cell %s/%s with %d output ports.\n", log_id(cell->type), log_id(module), log_id(cell), output_count); log_debug("Skipping %s cell %s/%s with %d output ports.\n", log_id(cell->type), log_id(module), log_id(cell), output_count);
return 0; return 0;
} }
@ -88,7 +88,7 @@ struct SplitfanoutWorker
auto bit_users = bit_users_db[outsig[0]]; auto bit_users = bit_users_db[outsig[0]];
for (int i = 0; i < GetSize(outsig); i++) { for (int i = 0; i < GetSize(outsig); i++) {
if (bit_users_db[outsig[i]] != bit_users) { if (bit_users_db[outsig[i]] != bit_users) {
log("Skipping %s cell %s/%s with bit-split output.\n", log_id(cell->type), log_id(module), log_id(cell)); log_debug("Skipping %s cell %s/%s with bit-split output.\n", log_id(cell->type), log_id(module), log_id(cell));
return 0; return 0;
} }
} }
@ -98,7 +98,7 @@ struct SplitfanoutWorker
return 0; return 0;
// Iterate over bit users and create a new cell for each one // Iterate over bit users and create a new cell for each one
log("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1); log_debug("Splitting %s cell %s/%s into %d copies based on fanout\n", log_id(cell->type), log_id(module), log_id(cell), GetSize(bit_users)-1);
int foi = 0; int foi = 0;
cell->unsetPort(outport); cell->unsetPort(outport);
for (auto bit_user : bit_users) for (auto bit_user : bit_users)

8
passes/opt/opt_balance_tree.cc
View file

@ -101,7 +101,7 @@ struct OptBalanceTreeWorker {
void find_chain_start_cells() { void find_chain_start_cells() {
for (auto cell : candidate_cells) { for (auto cell : candidate_cells) {
// Log candidate cell // Log candidate cell
log("Considering %s (%s)\n", log_id(cell), log_id(cell->type)); log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
// Get signals for cell ports // Get signals for cell ports
SigSpec a_sig = sigmap(cell->getPort(ID::A)); SigSpec a_sig = sigmap(cell->getPort(ID::A));
@ -172,7 +172,7 @@ struct OptBalanceTreeWorker {
} }
cell->setPort(inport, inport_sig); cell->setPort(inport, inport_sig);
cell->setParam(inport_width, GetSize(inport_sig)); cell->setParam(inport_width, GetSize(inport_sig));
log("Width reduced %s/%s by %d bits\n", log_id(cell), log_id(inport), bits_removed); log_debug("Width reduced %s/%s by %d bits\n", log_id(cell), log_id(inport), bits_removed);
} }
// Record number of bits removed from output // Record number of bits removed from output
@ -194,7 +194,7 @@ struct OptBalanceTreeWorker {
} }
cell->setPort(ID::Y, y_sig); cell->setPort(ID::Y, y_sig);
cell->setParam(ID::Y_WIDTH, GetSize(y_sig)); cell->setParam(ID::Y_WIDTH, GetSize(y_sig));
log("Width reduced %s/Y by %d bits\n", log_id(cell), bits_removed); log_debug("Width reduced %s/Y by %d bits\n", log_id(cell), bits_removed);
} }
} }
@ -207,7 +207,7 @@ struct OptBalanceTreeWorker {
Cell *mid_cell = chain[GetSize(chain) / 2]; Cell *mid_cell = chain[GetSize(chain) / 2];
Cell *midnext_cell = chain[GetSize(chain) / 2 + 1]; Cell *midnext_cell = chain[GetSize(chain) / 2 + 1];
Cell *end_cell = chain.back(); Cell *end_cell = chain.back();
log("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n", log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n",
GetSize(chain), log_id(mid_cell), log_id(midnext_cell), log_id(end_cell)); GetSize(chain), log_id(mid_cell), log_id(midnext_cell), log_id(end_cell));
// Get mid signals // Get mid signals