From e813624f21f2c6daa7af0befb50553bb668367fd Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Mar 2020 20:29:16 +0000
Subject: [PATCH 1/2] ice40: Map unmapped 'mince' DFFs to gate level

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ice40/synth_ice40.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 80bd05a84..b8aedaadf 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -345,6 +345,7 @@ struct SynthIce40Pass : public ScriptPass
 			if (min_ce_use >= 0) {
 				run("opt_merge");
 				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+				run("simplemap t:$dff");
 			}
 			run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");

From fa77fb857b42b32f3d518da8a590c406ddc8eee9 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Mar 2020 20:35:28 +0000
Subject: [PATCH 2/2] Add test for abc9+mince issue

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/various/ice40_mince_abc9.ys | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 tests/various/ice40_mince_abc9.ys

diff --git a/tests/various/ice40_mince_abc9.ys b/tests/various/ice40_mince_abc9.ys
new file mode 100644
index 000000000..408e16f05
--- /dev/null
+++ b/tests/various/ice40_mince_abc9.ys
@@ -0,0 +1,17 @@
+read_verilog <<EOT
+
+module top(input clk, ce, input [2:0] a, b, output reg [2:0] q);
+
+	reg [2:0] aa, bb;
+
+	always @(posedge clk) begin
+		if (ce) begin
+			aa <= a;
+		end
+		bb <= b;
+		q <= aa + bb;
+	end
+endmodule
+EOT
+
+synth_ice40 -abc9 -dffe_min_ce_use 4