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Use abc_{map,unmap,model}.v
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parent
c4d4c6db3f
commit
be9e4f1b67
8 changed files with 334 additions and 141 deletions
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@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
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{
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if (check_label("begin")) {
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if (vpr)
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run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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else
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run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
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run("read_verilog -lib -icells +/xilinx/cells_sim.v");
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run("read_verilog -lib +/xilinx/cells_xtra.v");
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@ -373,11 +373,11 @@ struct SynthXilinxPass : public ScriptPass
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}
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if (check_label("map_cells")) {
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std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
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std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
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if (widemux > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
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if (abc9)
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techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
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techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
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run("techmap " + techmap_args);
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run("clean");
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}
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@ -389,7 +389,7 @@ struct SynthXilinxPass : public ScriptPass
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else if (abc9) {
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if (family != "xc7")
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log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
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run("read_verilog -icells -lib +/xilinx/abc_ff.v");
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run("read_verilog -icells -lib +/xilinx/abc_model.v");
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if (nowidelut)
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run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
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else
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@ -408,7 +408,7 @@ struct SynthXilinxPass : public ScriptPass
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if (!nosrl || help_mode)
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run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
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if (abc9)
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run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
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run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
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else
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run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
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run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
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