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Use abc_{map,unmap,model}.v

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Eddie Hung 2019-08-20 12:39:11 -07:00
parent c4d4c6db3f
commit be9e4f1b67
8 changed files with 334 additions and 141 deletions
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8
techlibs/xilinx/cells_sim.v
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@ -169,14 +169,6 @@ module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
`ifdef _ABC
(* abc_box_id = 3, lib_whitebox *)
module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
assign O = S1 ? (S0 ? I3 : I2)
: (S0 ? I1 : I0);
endmodule
`endif
module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule