mirror of
https://github.com/YosysHQ/yosys
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Use abc_{map,unmap,model}.v
This commit is contained in:
Eddie Hung
parent
c4d4c6db3f
commit
be9e4f1b67
8 changed files with 334 additions and 141 deletions
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@ -39,7 +39,9 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
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120
techlibs/xilinx/abc_map.v
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120
techlibs/xilinx/abc_map.v
Normal file
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@ -0,0 +1,120 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
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module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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wire \$nextQ ;
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\$__ABC_FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_R_INVERTED(IS_R_INVERTED),
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.CLK_POLARITY(!IS_C_INVERTED),
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.EN_POLARITY(1'b1)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ ;
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\$__ABC_FDRE_1 #(
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.INIT(|0),
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.CLK_POLARITY(1'b0),
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.EN_POLARITY(1'b1)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED),
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.CLK_POLARITY(!IS_C_INVERTED),
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.EN_POLARITY(1'b1)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE_1 #(
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.INIT(INIT),
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.CLK_POLARITY(1'b0),
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.EN_POLARITY(1'b1)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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.CLK_POLARITY(!IS_C_INVERTED),
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.EN_POLARITY(1'b1)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDPE_1 #(
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.INIT(INIT),
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.CLK_POLARITY(1'b0),
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.EN_POLARITY(1'b1)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
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endmodule
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@ -20,93 +20,12 @@
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// ============================================================================
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// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
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module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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wire \$nextQ ;
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\$__ABC_FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_R_INVERTED(IS_R_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ ;
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\$__ABC_FDRE_1 #(.INIT(|0)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
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(* abc_box_id = 3, lib_whitebox *)
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module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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assign O = S1 ? (S0 ? I3 : I2)
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: (S0 ? I1 : I0);
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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\$__ABC_FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
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);
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\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
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\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
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endmodule
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`ifndef _ABC
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module \$__ABC_FF_ (input C, D, output Q);
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endmodule
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@ -114,7 +33,7 @@ endmodule
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module \$__ABC_ASYNC (input A, S, output Y);
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endmodule
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(* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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(* abc_box_id=1001, lib_whitebox, abc_flop *)
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module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -124,20 +43,24 @@ module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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parameter CLK_POLARITY = !IS_C_INVERTED;
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parameter EN_POLARITY = 1'b1;
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assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
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endmodule
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(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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(* abc_box_id=1002, lib_whitebox, abc_flop *)
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module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter CLK_POLARITY = 1'b0;
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parameter EN_POLARITY = 1'b1;
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assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
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endmodule
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(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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(* abc_box_id=1003, lib_whitebox, abc_flop *)
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module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -147,20 +70,24 @@ module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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parameter CLK_POLARITY = !IS_C_INVERTED;
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parameter EN_POLARITY = 1'b1;
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assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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(* abc_box_id=1004, lib_whitebox, abc_flop *)
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module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input CLR, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter CLK_POLARITY = 1'b0;
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parameter EN_POLARITY = 1'b1;
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assign Q = (CE && !CLR) ? D : \$pastQ ;
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endmodule
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(* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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(* abc_box_id=1005, lib_whitebox, abc_flop *)
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module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -170,17 +97,52 @@ module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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parameter CLK_POLARITY = !IS_C_INVERTED;
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parameter EN_POLARITY = 1'b1;
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assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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(* abc_box_id=1006, lib_whitebox, abc_flop *)
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module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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(* abc_flop_d *) input D,
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input PRE, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] INIT = 1'b0;
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parameter CLK_POLARITY = 1'b0;
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parameter EN_POLARITY = 1'b1;
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assign Q = (CE && !PRE) ? D : \$pastQ ;
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endmodule
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`endif
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module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
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output O;
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input I0, I1, I2, I3, S0, S1;
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wire T0, T1;
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parameter _TECHMAP_BITS_CONNMAP_ = 0;
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parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
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parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
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parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
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parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
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||||
parameter _TECHMAP_CONSTMSK_S0_ = 0;
|
||||
parameter _TECHMAP_CONSTVAL_S0_ = 0;
|
||||
parameter _TECHMAP_CONSTMSK_S1_ = 0;
|
||||
parameter _TECHMAP_CONSTVAL_S1_ = 0;
|
||||
if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
|
||||
assign T0 = I1;
|
||||
else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
|
||||
assign T0 = I0;
|
||||
else
|
||||
MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
|
||||
if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
|
||||
assign T1 = I3;
|
||||
else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
|
||||
assign T1 = I2;
|
||||
else
|
||||
MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
|
||||
if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
|
||||
assign O = T1;
|
||||
else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
|
||||
assign O = T0;
|
||||
else
|
||||
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
|
||||
endmodule
|
||||
140
techlibs/xilinx/abc_unmap.v
Normal file
140
techlibs/xilinx/abc_unmap.v
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
* 2019 Eddie Hung <eddie@fpgeh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
// ============================================================================
|
||||
|
||||
module \$__ABC_ASYNC (input A, S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FDRE (output Q,
|
||||
input C,
|
||||
input CE,
|
||||
input D,
|
||||
input R, \$pastQ );
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_R_INVERTED = 1'b0;
|
||||
parameter CLK_POLARITY = !IS_C_INVERTED;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
|
||||
FDRE #(
|
||||
.INIT(INIT),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_R_INVERTED(IS_R_INVERTED),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FDRE_1 (output Q,
|
||||
input C,
|
||||
input CE,
|
||||
input D,
|
||||
input R, \$pastQ );
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter CLK_POLARITY = 1'b0;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
|
||||
|
||||
FDRE_1 #(
|
||||
.INIT(INIT),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .R(R)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FDCE (output Q,
|
||||
input C,
|
||||
input CE,
|
||||
input D,
|
||||
input CLR, \$pastQ );
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CLR_INVERTED = 1'b0;
|
||||
parameter CLK_POLARITY = !IS_C_INVERTED;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
|
||||
FDCE #(
|
||||
.INIT(INIT),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_CLR_INVERTED(IS_CLR_INVERTED),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FDCE_1 (output Q,
|
||||
input C,
|
||||
input CE,
|
||||
input D,
|
||||
input CLR, \$pastQ );
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter CLK_POLARITY = 1'b0;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
|
||||
FDCE_1 #(
|
||||
.INIT(INIT),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FDPE (output Q,
|
||||
input C,
|
||||
input CE,
|
||||
input D,
|
||||
input PRE, \$pastQ );
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter [0:0] IS_C_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_D_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_PRE_INVERTED = 1'b0;
|
||||
parameter CLK_POLARITY = !IS_C_INVERTED;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
|
||||
FDPE #(
|
||||
.INIT(INIT),
|
||||
.IS_C_INVERTED(IS_C_INVERTED),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_PRE_INVERTED(IS_PRE_INVERTED),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_FDPE_1 (output Q,
|
||||
input C,
|
||||
input CE,
|
||||
input D,
|
||||
input PRE, \$pastQ );
|
||||
parameter [0:0] INIT = 1'b0;
|
||||
parameter CLK_POLARITY = 1'b0;
|
||||
parameter EN_POLARITY = 1'b1;
|
||||
|
||||
FDPE_1 #(
|
||||
.INIT(INIT),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
);
|
||||
endmodule
|
||||
|
|
@ -331,7 +331,6 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y)
|
|||
endmodule
|
||||
`endif
|
||||
|
||||
`ifndef _ABC
|
||||
module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
|
||||
output O;
|
||||
input I0, I1, I2, I3, S0, S1;
|
||||
|
|
@ -364,4 +363,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
|
|||
else
|
||||
MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));
|
||||
endmodule
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -169,14 +169,6 @@ module MUXF8(output O, input I0, I1, S);
|
|||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
||||
`ifdef _ABC
|
||||
(* abc_box_id = 3, lib_whitebox *)
|
||||
module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
|
||||
assign O = S1 ? (S0 ? I3 : I2)
|
||||
: (S0 ? I1 : I0);
|
||||
endmodule
|
||||
`endif
|
||||
|
||||
module XORCY(output O, input CI, LI);
|
||||
assign O = CI ^ LI;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
{
|
||||
if (check_label("begin")) {
|
||||
if (vpr)
|
||||
run("read_verilog -lib -icells -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
|
||||
run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
|
||||
else
|
||||
run("read_verilog -lib -icells -D _ABC +/xilinx/cells_sim.v");
|
||||
run("read_verilog -lib -icells +/xilinx/cells_sim.v");
|
||||
|
||||
run("read_verilog -lib +/xilinx/cells_xtra.v");
|
||||
|
||||
|
|
@ -373,11 +373,11 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
if (check_label("map_cells")) {
|
||||
std::string techmap_args = "-map +/techmap.v -D _ABC -map +/xilinx/cells_map.v";
|
||||
std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
|
||||
if (widemux > 0)
|
||||
techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
|
||||
if (abc9)
|
||||
techmap_args += " -map +/xilinx/ff_map.v -D _ABC -map +/xilinx/abc_ff.v";
|
||||
techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
|
||||
run("techmap " + techmap_args);
|
||||
run("clean");
|
||||
}
|
||||
|
|
@ -389,7 +389,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
else if (abc9) {
|
||||
if (family != "xc7")
|
||||
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
|
||||
run("read_verilog -icells -lib +/xilinx/abc_ff.v");
|
||||
run("read_verilog -icells -lib +/xilinx/abc_model.v");
|
||||
if (nowidelut)
|
||||
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
|
||||
else
|
||||
|
|
@ -408,7 +408,7 @@ struct SynthXilinxPass : public ScriptPass
|
|||
if (!nosrl || help_mode)
|
||||
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
|
||||
if (abc9)
|
||||
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
|
||||
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/abc_unmap.v");
|
||||
else
|
||||
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
|
||||
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue