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https://github.com/YosysHQ/yosys
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cleanup
This commit is contained in:
Alain Dargelas
parent
c7623e4850
commit
be95a08c08
1 changed files with 122 additions and 132 deletions
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@ -97,6 +97,112 @@ bool isSigSpecUsedIn(SigSpec &haystack, SigMap &sigmap, SigSpec &needle)
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return match;
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}
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// Remove a buffer and fix the fanout connections to use the buffer's input
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void removeBuffer(Module *module, SigMap &sigmap, std::set<Cell *>& fanoutcells, Cell *buffer, bool debug)
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{
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if (debug)
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std::cout << "Buffer with fanout 1: " << buffer->name.c_str() << std::endl;
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RTLIL::SigSpec bufferInSig = buffer->getPort(ID::A);
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RTLIL::SigSpec bufferOutSig = buffer->getPort(ID::Y);
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// Find which cell use that buffer's output and reconnect its input to the former cell (buffer's input)
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for (Cell *c : fanoutcells) {
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bool reconnected = false;
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if (debug)
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std::cout << " Cell in its fanout: " << c->name.c_str() << std::endl;
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for (auto &conn : c->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (c->input(portName)) {
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if (actual.is_chunk()) {
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// Input is a chunk
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if (bufferOutSig == sigmap(actual)) {
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// Input is one of the cell's outputs, its a match
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if (debug)
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std::cout << " Replace: " << getParentWire(bufferOutSig)->name.c_str() << " by "
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<< getParentWire(bufferInSig)->name.c_str() << std::endl;
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// Override cell's input with original buffer's input
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c->setPort(portName, bufferInSig);
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reconnected = true;
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break;
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}
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} else {
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// Input is a vector of chunks
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if (isSigSpecUsedIn(actual, sigmap, bufferOutSig)) {
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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if (sigmap(SigSpec(chunk)) == sigmap(bufferOutSig)) {
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if (debug)
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std::cout << " Replace: " << getParentWire(bufferOutSig)->name.c_str()
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<< " by " << getParentWire(bufferInSig)->name.c_str() << std::endl;
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newChunks.push_back(bufferInSig.as_chunk());
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} else {
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newChunks.push_back(chunk);
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}
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}
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c->setPort(portName, newChunks);
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reconnected = true;
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break;
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}
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}
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}
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}
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if (reconnected)
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break;
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}
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// Delete the now unsused buffer and it's output signal
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module->remove(buffer);
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module->remove({bufferOutSig.as_wire()});
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}
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RTLIL::SigSpec getCellOutputSigSpec(Cell* cell, SigMap& sigmap) {
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RTLIL::SigSpec cellOutSig;
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (cell->output(portName)) {
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cellOutSig = sigmap(actual);
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break;
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}
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}
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return cellOutSig;
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}
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// Get new output signal for a given signal, used all datastructures with change to buffer
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SigSpec updateToBuffer(std::map<SigSpec, int>& bufferIndexes, std::map<RTLIL::SigSpec,
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>>>& buffer_outputs,
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dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout,
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std::map<Cell *, int>& bufferActualFanout, int max_output_per_buffer, Cell* cell, SigSpec sigToReplace, bool debug)
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{
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if (debug)
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std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[sigToReplace] << " buffer_outputs " << buffer_outputs[sigToReplace].size()
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<< std::endl;
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// Retrieve the buffer information for that cell's chunk
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> &buf_info_vec = buffer_outputs[sigToReplace];
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// Retrieve which buffer is getting filled
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int bufferIndex = bufferIndexes[sigToReplace];
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std::tuple<RTLIL::SigSpec, Cell *> &buf_info = buf_info_vec[bufferIndex];
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SigSpec newSig = std::get<0>(buf_info);
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Cell *newBuf = std::get<1>(buf_info);
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// Keep track of fanout map information for recursive calls
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sig2CellsInFanout[newSig].insert(cell);
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// Increment buffer capacity
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bufferActualFanout[newBuf]++;
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if (debug)
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std::cout << " USE: " << newBuf->name.c_str() << " fanout: " << bufferActualFanout[newBuf] << std::endl;
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// If we reached capacity for a given buffer, move to the next buffer
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if (bufferActualFanout[newBuf] >= max_output_per_buffer) {
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if (debug)
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std::cout << " REACHED MAX" << std::endl;
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if (int(buffer_outputs[sigToReplace].size() - 1) > bufferIndex) {
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bufferIndexes[sigToReplace]++;
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if (debug)
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std::cout << " NEXT BUFFER" << std::endl;
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}
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}
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// Return buffer's output
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return newSig;
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}
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// For a given cell with fanout exceeding the limit,
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// - create an array of buffers per cell output chunk (2 dimentions array of buffers)
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// - connect cell chunk to corresponding buffers
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@ -134,15 +240,7 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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}
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// Get cell output
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RTLIL::SigSpec cellOutSig;
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for (auto &conn : cell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (cell->output(portName)) {
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cellOutSig = sigmap(actual);
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break;
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}
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}
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RTLIL::SigSpec cellOutSig = getCellOutputSigSpec(cell, sigmap);
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// Keep track of the fanout count for each new buffer
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std::map<Cell *, int> bufferActualFanout;
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@ -151,7 +249,7 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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// Keep track of which buffer in the array is getting filled for a given chunk
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std::map<SigSpec, int> bufferIndexes;
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// Create buffers and new wires
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// Create new buffers and new wires
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for (SigChunk chunk : cellOutSig.chunks()) {
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> buffer_chunk_outputs;
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for (int i = 0; i < num_buffers; ++i) {
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@ -168,108 +266,53 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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}
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// Cumulate all cells in the fanout of this cell
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std::set<Cell *> cells = sig2CellsInFanout[cellOutSig];
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std::set<Cell *> fanoutcells = sig2CellsInFanout[cellOutSig];
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for (int i = 0; i < cellOutSig.size(); i++) {
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SigSpec bit_sig = cellOutSig.extract(i, 1);
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for (Cell *c : sig2CellsInFanout[sigmap(bit_sig)]) {
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cells.insert(c);
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fanoutcells.insert(c);
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}
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}
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// Fix input connections to cells in fanout of buffer to point to the inserted buffer
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for (Cell *c : cells) {
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for (Cell *fanoutcell : fanoutcells) {
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if (debug)
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std::cout << "\n CELL in fanout: " << c->name.c_str() << "\n" << std::flush;
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for (auto &conn : c->connections()) {
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std::cout << "\n CELL in fanout: " << fanoutcell->name.c_str() << "\n" << std::flush;
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for (auto &conn : fanoutcell->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = sigmap(conn.second);
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if (c->input(portName)) {
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if (fanoutcell->input(portName)) {
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if (actual.is_chunk()) {
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// Input of that cell is a chunk
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if (debug)
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std::cout << " IS A CHUNK" << std::endl;
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if (buffer_outputs.find(actual) != buffer_outputs.end()) {
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// Input is one of the cell's outputs, its a match
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if (debug)
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std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[actual] << " buffer_outputs "
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<< buffer_outputs[actual].size() << std::endl;
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// Retrieve the buffer information for that cell's chunk
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> &buf_info_vec = buffer_outputs[actual];
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// Retrieve which buffer is getting filled
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int bufferIndex = bufferIndexes[actual];
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std::tuple<RTLIL::SigSpec, Cell *> &buf_info = buf_info_vec[bufferIndex];
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SigSpec newSig = std::get<0>(buf_info);
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Cell *newBuf = std::get<1>(buf_info);
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SigSpec newSig = updateToBuffer(bufferIndexes, buffer_outputs, sig2CellsInFanout,
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bufferActualFanout, max_output_per_buffer, fanoutcell, actual, debug);
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// Override the fanout cell's input with the buffer output
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c->setPort(portName, newSig);
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// Keep track of fanout map information for recursive calls
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sig2CellsInFanout[newSig].insert(c);
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// Increment buffer capacity
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bufferActualFanout[newBuf]++;
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if (debug)
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std::cout << " USE: " << newBuf->name.c_str() << " fanout: " << bufferActualFanout[newBuf]
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<< std::endl;
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// If we reached capacity for a given buffer, move to the next buffer
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if (bufferActualFanout[newBuf] >= max_output_per_buffer) {
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if (debug)
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std::cout << " REACHED MAX" << std::endl;
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if (int(buffer_outputs[actual].size() - 1) > bufferIndex) {
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bufferIndexes[actual]++;
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if (debug)
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std::cout << " NEXT BUFFER" << std::endl;
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}
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}
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fanoutcell->setPort(portName, newSig);
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}
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} else {
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// Input of that cell is a list of chunks
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if (debug)
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std::cout << " NOT A CHUNK" << std::endl;
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if (isSigSpecUsedIn(actual, sigmap, cellOutSig)) {
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if (debug)
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std::cout << " MATCH" << std::endl;
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// Create a new chunk vector
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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bool replacedChunk = false;
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if (buffer_outputs.find(chunk) != buffer_outputs.end()) {
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if (debug)
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std::cout << " CHUNK, indexCurrentBuffer: " << bufferIndexes[chunk]
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<< " buffer_outputs " << buffer_outputs[chunk].size() << std::endl;
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// Retrieve the buffer information for that cell's chunk
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std::vector<std::tuple<RTLIL::SigSpec, Cell *>> &buf_info_vec = buffer_outputs[chunk];
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// Retrieve which buffer is getting filled
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int bufferIndex = bufferIndexes[chunk];
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std::tuple<RTLIL::SigSpec, Cell *> &buf_info = buf_info_vec[bufferIndex];
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SigSpec newSig = std::get<0>(buf_info);
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Cell *newBuf = std::get<1>(buf_info);
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SigSpec newSig = updateToBuffer(bufferIndexes, buffer_outputs, sig2CellsInFanout,
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bufferActualFanout, max_output_per_buffer, fanoutcell, chunk, debug);
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// Append the buffer's output in the chunk vector
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newChunks.push_back(newSig.as_chunk());
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// Keep track of fanout map information for recursive calls
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sig2CellsInFanout[newSig].insert(c);
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replacedChunk = true;
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// Increment buffer capacity
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bufferActualFanout[newBuf]++;
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if (debug)
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std::cout << " USE: " << newBuf->name.c_str()
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<< " fanout: " << bufferActualFanout[newBuf] << std::endl;
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// If we reached capacity for a given buffer, move to the next buffer
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if (bufferActualFanout[newBuf] >= max_output_per_buffer) {
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if (debug)
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std::cout << " REACHED MAX" << std::endl;
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if (int(buffer_outputs[chunk].size() - 1) > bufferIndex) {
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bufferIndexes[chunk]++;
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if (debug)
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std::cout << " NEXT BUFFER" << std::endl;
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}
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}
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}
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if (!replacedChunk) {
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} else {
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// Append original chunk if no buffer used
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newChunks.push_back(chunk);
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}
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}
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// Override the fanout cell's input with the newly created chunk vector
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c->setPort(portName, newChunks);
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fanoutcell->setPort(portName, newChunks);
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break;
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}
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}
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@ -281,60 +324,7 @@ void fixfanout(RTLIL::Design *design, RTLIL::Module *module, SigMap &sigmap, dic
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for (std::map<Cell *, int>::iterator itr = bufferActualFanout.begin(); itr != bufferActualFanout.end(); itr++) {
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if (itr->second == 1) {
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// Remove previously inserted buffers with fanout of 1 (Hard to predict the last buffer usage in above step)
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if (debug)
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std::cout << "Buffer with fanout 1: " << itr->first->name.c_str() << std::endl;
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RTLIL::SigSpec bufferInSig = itr->first->getPort(ID::A);
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RTLIL::SigSpec bufferOutSig = itr->first->getPort(ID::Y);
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// Find which cell use that buffer's output and reconnect its input to the former cell (buffer's input)
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for (Cell *c : cells) {
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bool reconnected = false;
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if (debug)
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std::cout << " Cell in its fanout: " << c->name.c_str() << std::endl;
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for (auto &conn : c->connections()) {
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IdString portName = conn.first;
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RTLIL::SigSpec actual = conn.second;
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if (c->input(portName)) {
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if (actual.is_chunk()) {
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// Input is a chunk
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if (bufferOutSig == sigmap(actual)) {
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// Input is one of the cell's outputs, its a match
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if (debug)
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std::cout << " Replace: " << getParentWire(bufferOutSig)->name.c_str()
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<< " by " << getParentWire(bufferInSig)->name.c_str() << std::endl;
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// Override cell's input with original buffer's input
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c->setPort(portName, bufferInSig);
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reconnected = true;
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break;
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}
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} else {
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// Input is a vector of chunks
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if (isSigSpecUsedIn(actual, sigmap, bufferOutSig)) {
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std::vector<RTLIL::SigChunk> newChunks;
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for (SigChunk chunk : actual.chunks()) {
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if (sigmap(SigSpec(chunk)) == sigmap(bufferOutSig)) {
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if (debug)
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std::cout
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<< " Replace: "
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<< getParentWire(bufferOutSig)->name.c_str() << " by "
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<< getParentWire(bufferInSig)->name.c_str() << std::endl;
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newChunks.push_back(bufferInSig.as_chunk());
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} else {
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newChunks.push_back(chunk);
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}
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}
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c->setPort(portName, newChunks);
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reconnected = true;
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break;
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}
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}
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}
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}
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if (reconnected)
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break;
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}
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// Delete the now unsused buffer and it's output signal
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module->remove(itr->first);
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module->remove({bufferOutSig.as_wire()});
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removeBuffer(module, sigmap, fanoutcells, itr->first, debug);
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} else {
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// Recursively fix the fanout of the newly created buffers
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fixfanout(design, module, sigmap, sig2CellsInFanout, itr->first, itr->second, limit, debug);
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