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fixup! refactor

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This commit is contained in:
Emil J. Tywoniak 2025-08-15 11:13:45 +02:00
parent 436d698525
commit be956f3416
1 changed files with 0 additions and 1 deletions
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kernel/rtlil.cc
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@ -4133,7 +4133,6 @@ void RTLIL::Module::bufNormalize()
if (GetSize(sig) == 0) continue;
if (sig.is_wire()) {
log_error("unreachable");
Detail::drive(sig.as_wire(), {cell, portname});
continue;
}