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fixup! refactor
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@ -4133,7 +4133,6 @@ void RTLIL::Module::bufNormalize()
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if (GetSize(sig) == 0) continue;
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if (sig.is_wire()) {
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log_error("unreachable");
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Detail::drive(sig.as_wire(), {cell, portname});
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continue;
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}
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