3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-09 23:53:26 +00:00

Docs: Less leading backslashes

This commit is contained in:
Krystine Sherwin 2024-05-27 16:02:17 +12:00
parent 2b4a4cb536
commit be5572ca0e
No known key found for this signature in database
2 changed files with 9 additions and 9 deletions

View file

@ -196,7 +196,7 @@ Removing unused cells and wires - `opt_clean` pass
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
This pass identifies unused signals and cells and removes them from the design.
It also creates an ``\unused_bits`` attribute on wires with unused bits. This
It also creates an ``unused_bits`` attribute on wires with unused bits. This
attribute can be used for debugging or by other optimization passes.
When to use `opt` or `clean`