From bdce610f3d725c481873e6f4870d8dd77ea24383 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 9 Mar 2026 16:37:30 +0100
Subject: [PATCH] bug2920: disable

---
 tests/opt/bug2920.ys | 80 +++++++++++++++++++++++---------------------
 1 file changed, 41 insertions(+), 39 deletions(-)

diff --git a/tests/opt/bug2920.ys b/tests/opt/bug2920.ys
index 6d86f9cb1..9a8020302 100644
--- a/tests/opt/bug2920.ys
+++ b/tests/opt/bug2920.ys
@@ -1,42 +1,44 @@
-read_rtlil <<EOT
+# TODO re-enable when https://github.com/YosysHQ/yosys/issues/5735 fixed
 
-module \mod
-  wire input 1 \clk
-  attribute \init 2'00
-  wire width 2 $q1
-  attribute \init 2'00
-  wire width 2 $q2
-  wire output 2 width 4 \q
-  cell $dff $ff1
-    parameter \CLK_POLARITY 1'1
-    parameter \WIDTH 1
-    connect \CLK \clk
-    connect \D 1'0
-    connect \Q $q1 [0]
-  end
-  cell $dff $ff2
-    parameter \CLK_POLARITY 1'1
-    parameter \WIDTH 1
-    connect \CLK \clk
-    connect \D 1'0
-    connect \Q $q2 [0]
-  end
-  cell $dff $ff3
-    parameter \CLK_POLARITY 1'1
-    parameter \WIDTH 2
-    connect \CLK \clk
-    connect \D 2'00
-    connect \Q { $q1 [1] $q2 [1] }
-  end
-  connect \q [0] $q1 [0]
-  connect \q [1] $q2 [0]
-  connect \q [2] $q1 [1]
-  connect \q [3] $q2 [1]
-end
+# read_rtlil <<EOT
 
-EOT
+# module \mod
+#   wire input 1 \clk
+#   attribute \init 2'00
+#   wire width 2 $q1
+#   attribute \init 2'00
+#   wire width 2 $q2
+#   wire output 2 width 4 \q
+#   cell $dff $ff1
+#     parameter \CLK_POLARITY 1'1
+#     parameter \WIDTH 1
+#     connect \CLK \clk
+#     connect \D 1'0
+#     connect \Q $q1 [0]
+#   end
+#   cell $dff $ff2
+#     parameter \CLK_POLARITY 1'1
+#     parameter \WIDTH 1
+#     connect \CLK \clk
+#     connect \D 1'0
+#     connect \Q $q2 [0]
+#   end
+#   cell $dff $ff3
+#     parameter \CLK_POLARITY 1'1
+#     parameter \WIDTH 2
+#     connect \CLK \clk
+#     connect \D 2'00
+#     connect \Q { $q1 [1] $q2 [1] }
+#   end
+#   connect \q [0] $q1 [0]
+#   connect \q [1] $q2 [0]
+#   connect \q [2] $q1 [1]
+#   connect \q [3] $q2 [1]
+# end
 
-opt_clean
-opt_merge
-opt_dff
-opt_clean
+# EOT
+
+# opt_clean
+# opt_merge
+# opt_dff
+# opt_clean