mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity

Fix existing tests/liberty tests, and add them to Makefile.

Browse source
This commit is contained in:
Sean Luchen 2025-04-03 09:56:24 -07:00
parent 4610889d27
commit bdcbbf2db6
10 changed files with 68 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/liberty/semicolmissing.lib.verilogsim.ok
View file

@ -3,7 +3,7 @@ module fulladder (A, B, CI, CO, Y);
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
assign Y = ((A^B)^CI); // "((A^B)^CI)"
endmodule