mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity

Fix existing tests/liberty tests, and add them to Makefile.

Browse source
This commit is contained in:
Sean Luchen 2025-04-03 09:56:24 -07:00
parent 4610889d27
commit bdcbbf2db6
10 changed files with 68 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

60
tests/liberty/normal.lib.verilogsim.ok
View file

@ -1,86 +1,86 @@
module inv (A, Y);
input A;
output Y;
assign Y = ~A; // A'
assign Y = ~A; // "A'"
endmodule
module tri_inv (A, S, Z);
input A;
input S;
output Z;
assign Z = ~A; // A'
assign Z = ~A; // "A'"
endmodule
module buffer (A, Y);
input A;
output Y;
assign Y = A; // A
assign Y = A; // "A"
endmodule
module nand2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A&B); // (A * B)'
assign Y = ~(A&B); // "(A * B)'"
endmodule
module nor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = ~(A|B); // (A + B)'
assign Y = ~(A|B); // "(A + B)'"
endmodule
module xor2 (A, B, Y);
input A;
input B;
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
endmodule
module imux2 (A, B, S, Y);
input A;
input B;
input S;
output Y;
assign Y = ~(&(A&S)|(B&~S)&); // ( (A * S) + (B * S') )'
assign Y = ~(&(A&S)|(B&~S)&); // "( (A * S) + (B * S') )'"
endmodule
module dff (D, CLK, RESET, PRESET, Q, QN);
reg IQ, IQN;
reg "IQ", "IQN";
input D;
input CLK;
input RESET;
input PRESET;
output Q;
assign Q = IQ; // IQ
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // IQN
assign QN = IQN; // "IQN"
always @(posedge CLK, posedge RESET, posedge PRESET) begin
if ((RESET) && (PRESET)) begin
IQ <= 0;
IQN <= 0;
"IQ" <= 0;
"IQN" <= 0;
end
else if (RESET) begin
IQ <= 0;
IQN <= 1;
"IQ" <= 0;
"IQN" <= 1;
end
else if (PRESET) begin
IQ <= 1;
IQN <= 0;
"IQ" <= 1;
"IQN" <= 0;
end
else begin
// D
IQ <= D;
IQN <= ~(D);
// "D"
"IQ" <= D;
"IQN" <= ~(D);
end
end
endmodule
module latch (D, G, Q, QN);
reg IQ, IQN;
reg "IQ", "IQN";
input D;
input G;
output Q;
assign Q = IQ; // IQ
assign Q = IQ; // "IQ"
output QN;
assign QN = IQN; // IQN
assign QN = IQN; // "IQN"
always @* begin
if (G) begin
IQ <= D;
IQN <= ~(D);
"IQ" <= D;
"IQN" <= ~(D);
end
end
endmodule
@ -89,29 +89,29 @@ module aoi211 (A, B, C, Y);
input B;
input C;
output Y;
assign Y = ~((A&B)|C); // ((A * B) + C)'
assign Y = ~((A&B)|C); // "((A * B) + C)'"
endmodule
module oai211 (A, B, C, Y);
input A;
input B;
input C;
output Y;
assign Y = ~((A|B)&C); // ((A + B) * C)'
assign Y = ~((A|B)&C); // "((A + B) * C)'"
endmodule
module halfadder (A, B, C, Y);
input A;
input B;
output C;
assign C = (A&B); // (A * B)
assign C = (A&B); // "(A * B)"
output Y;
assign Y = (A&~B)|(~A&B); // (A *B') + (A' * B)
assign Y = (A&~B)|(~A&B); // "(A *B') + (A' * B)"
endmodule
module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // (((A * B)+(B * CI))+(CI * A))
assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
output Y;
assign Y = ((A^B)^CI); // ((A^B)^CI)
assign Y = ((A^B)^CI); // "((A^B)^CI)"
endmodule