mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-29 11:55:52 +00:00
Code Activity

Fix existing tests/liberty tests, and add them to Makefile.

Browse source
This commit is contained in:
Sean Luchen 2025-04-03 09:56:24 -07:00
parent 4610889d27
commit bdcbbf2db6
10 changed files with 68 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tests/liberty/XNOR2X1.lib.verilogsim.ok
View file

@ -2,5 +2,5 @@ module XNOR2X1 (B, A, Y);
input B;
input A;
output Y;
assign Y = !(B&!A|!B&A); // !(B&!A|!B&A)
assign Y = !(B&!A|!B&A); // "!(B&!A|!B&A)"
endmodule