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Add left and right bound properties to wire. Add test. Fix printing

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for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
This commit is contained in:
Roland Coeurjoly 2024-08-21 16:21:29 +02:00
parent 27c1432253
commit bdc43c6592
6 changed files with 40 additions and 3 deletions
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13
frontends/verific/verific.cc
View file

@ -450,6 +450,19 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
auto type_range = nl->GetTypeRange(obj->Name());
if (!type_range)
return;
if (type_range->IsTypeScalar()) {
const long long bottom_bound = type_range->GetScalarRangeLeftBound();
const long long top_bound = type_range->GetScalarRangeRightBound();
const unsigned bit_width = type_range->NumElements();
RTLIL::Const bottom_const(bottom_bound, bit_width);
RTLIL::Const top_const(top_bound, bit_width);
if (bottom_bound < 0 || top_bound < 0) {
bottom_const.flags |= RTLIL::CONST_FLAG_SIGNED;
top_const.flags |= RTLIL::CONST_FLAG_SIGNED;
}
attributes.emplace(ID(bottom_bound), bottom_const);
attributes.emplace(ID(top_bound), top_const);
}
if (!type_range->IsTypeEnum())
return;
#ifdef VERIFIC_VHDL_SUPPORT

2
kernel/rtlil.cc
View file

@ -213,7 +213,7 @@ RTLIL::Const::Const(const std::string &str)
}
}
RTLIL::Const::Const(int val, int width)
RTLIL::Const::Const(long long val, int width)
{
flags = RTLIL::CONST_FLAG_NONE;
bits.reserve(width);

2
kernel/rtlil.h
View file

@ -662,7 +662,7 @@ struct RTLIL::Const
Const() : flags(RTLIL::CONST_FLAG_NONE) {}
Const(const std::string &str);
Const(int val, int width = 32);
Const(long long val, int width = 32);
Const(RTLIL::State bit, int width = 1);
Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }
Const(const std::vector<bool> &bits);

2
passes/cmds/printattrs.cc
View file

@ -42,7 +42,7 @@ struct PrintAttrsPass : public Pass {
static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
if (x.flags == RTLIL::CONST_FLAG_STRING)
log("%s(* %s=\"%s\" *)\n", get_indent_str(indent).c_str(), log_id(s), x.decode_string().c_str());
else if (x.flags == RTLIL::CONST_FLAG_NONE)
else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
log("%s(* %s=%s *)\n", get_indent_str(indent).c_str(), log_id(s), x.as_string().c_str());
else
log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail

18
tests/verific/bounds.vhd Normal file
View file

@ -0,0 +1,18 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity work is
Port (
a : in INTEGER range -5 to 10;
b : out INTEGER range -6 to 11
);
end entity work;
architecture Behavioral of work is
begin
process(a)
begin
b <= a;
end process;
end architecture Behavioral;

6
tests/verific/bounds.ys Normal file
View file

@ -0,0 +1,6 @@
read -vhdl bounds.vhd
verific -import work
select -assert-count 1 a:bottom_bound=5'bs11011
select -assert-count 1 a:top_bound=5'bs01010
select -assert-count 1 a:bottom_bound=5'bs11010
select -assert-count 1 a:top_bound=5'bs01011