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Add left and right bound properties to wire. Add test. Fix printing

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Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
This commit is contained in:
Roland Coeurjoly 2024-08-21 16:21:29 +02:00
parent 27c1432253
commit bdc43c6592
6 changed files with 40 additions and 3 deletions
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6
tests/verific/bounds.ys Normal file
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read -vhdl bounds.vhd
verific -import work
select -assert-count 1 a:bottom_bound=5'bs11011
select -assert-count 1 a:top_bound=5'bs01010
select -assert-count 1 a:bottom_bound=5'bs11010
select -assert-count 1 a:top_bound=5'bs01011