3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00

Added $anyseq cell type

This commit is contained in:
Clifford Wolf 2016-10-14 15:24:03 +02:00
parent 2733994aeb
commit bdc316db50
11 changed files with 40 additions and 11 deletions

View file

@ -1108,6 +1108,7 @@ public:
RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d);
RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1);
RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1);
RTLIL::SigSpec Initstate (RTLIL::IdString name);
};