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Added $anyseq cell type

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This commit is contained in:
Clifford Wolf 2016-10-14 15:24:03 +02:00
parent 2733994aeb
commit bdc316db50
11 changed files with 40 additions and 11 deletions
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11
kernel/rtlil.cc
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@ -1037,7 +1037,7 @@ namespace {
return;
}
if (cell->type == "$anyconst") {
if (cell->type.in("$anyconst", "$anyseq")) {
port("\\Y", param("\\WIDTH"));
check_expected();
return;
@ -2009,6 +2009,15 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
return sig;
}
RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width)
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, "$anyseq");
cell->setParam("\\WIDTH", width);
cell->setPort("\\Y", sig);
return sig;
}
RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
{
RTLIL::SigSpec sig = addWire(NEW_ID);