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async2sync: Refactor to use FfInitVals.

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This commit is contained in:
Marcelina Kościelnicka 2020-07-19 03:25:30 +02:00
parent c9251eb26b
commit bd959d5d9e
1 changed files with 11 additions and 53 deletions
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64
passes/sat/async2sync.cc
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@ -19,6 +19,7 @@
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/ffinit.h"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -62,19 +63,7 @@ struct Async2syncPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SigMap sigmap(module); SigMap sigmap(module);
dict<SigBit, State> initbits; FfInitVals initvals(&sigmap, module);
pool<SigBit> del_initbits;
for (auto wire : module->wires())
if (wire->attributes.count(ID::init) > 0)
{
Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
initbits[initsig[i]] = initval[i];
}
for (auto cell : vector<Cell*>(module->selected_cells())) for (auto cell : vector<Cell*>(module->selected_cells()))
{ {
@ -93,16 +82,12 @@ struct Async2syncPass : public Pass {
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q)); log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q));
Const init_val; Const init_val = initvals(sig_q);
for (int i = 0; i < GetSize(sig_q); i++) { initvals.remove_init(sig_q);
SigBit bit = sigmap(sig_q[i]);
init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
del_initbits.insert(bit);
}
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
new_q->attributes[ID::init] = init_val; initvals.set_init(new_q, init_val);
if (arst_pol) { if (arst_pol) {
module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d); module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
@ -137,16 +122,12 @@ struct Async2syncPass : public Pass {
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
log_signal(sig_set), log_signal(sig_clr), log_signal(sig_d), log_signal(sig_q)); log_signal(sig_set), log_signal(sig_clr), log_signal(sig_d), log_signal(sig_q));
Const init_val; Const init_val = initvals(sig_q);
for (int i = 0; i < GetSize(sig_q); i++) { initvals.remove_init(sig_q);
SigBit bit = sigmap(sig_q[i]);
init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
del_initbits.insert(bit);
}
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
new_q->attributes[ID::init] = init_val; initvals.set_init(new_q, init_val);
if (!set_pol) if (!set_pol)
sig_set = module->Not(NEW_ID, sig_set); sig_set = module->Not(NEW_ID, sig_set);
@ -182,15 +163,11 @@ struct Async2syncPass : public Pass {
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
log_signal(sig_en), log_signal(sig_d), log_signal(sig_q)); log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
Const init_val; Const init_val = initvals(sig_q);
for (int i = 0; i < GetSize(sig_q); i++) { initvals.remove_init(sig_q);
SigBit bit = sigmap(sig_q[i]);
init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
del_initbits.insert(bit);
}
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
new_q->attributes[ID::init] = init_val; initvals.set_init(new_q, init_val);
if (en_pol) { if (en_pol) {
module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q); module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
@ -206,25 +183,6 @@ struct Async2syncPass : public Pass {
continue; continue;
} }
} }
for (auto wire : module->wires())
if (wire->attributes.count(ID::init) > 0)
{
bool delete_initattr = true;
Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
if (del_initbits.count(initsig[i]) > 0)
initval[i] = State::Sx;
else if (initval[i] != State::Sx)
delete_initattr = false;
if (delete_initattr)
wire->attributes.erase(ID::init);
else
wire->attributes.at(ID::init) = initval;
}
} }
} }
} Async2syncPass; } Async2syncPass;