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connect: remove input ports on conflict

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This commit is contained in:
Emil J. Tywoniak 2026-03-24 22:39:45 +01:00
parent aecc173f83
commit bd8738de15
1 changed files with 15 additions and 1 deletions
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16
passes/cmds/connect.cc
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@ -32,11 +32,23 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
// (void)module->connections(); // trigger signorm flush
for (auto cell : module->cells()) for (auto cell : module->cells())
for (auto &port : cell->connections_) for (auto &port : cell->connections_)
if (ct.cell_output(cell->type, port.first)) if (ct.cell_output(cell->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second); sigmap(port.second).replace(sig, dummy_wire, &port.second);
bool need_fixup = false;
for (auto bit : sig.bits()) {
if (bit.is_wire() && bit.wire->port_input) {
bit.wire->port_input = false;
need_fixup = true;
}
}
if (need_fixup)
module->fixup_ports();
for (auto &conn : module->connections_) for (auto &conn : module->connections_)
sigmap(conn.first).replace(sig, dummy_wire, &conn.first); sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
} }
@ -66,7 +78,7 @@ struct ConnectPass : public Pass {
log("\n"); log("\n");
log("\n"); log("\n");
log("Per default signal alias names are resolved and all signal names are mapped\n"); log("Per default signal alias names are resolved and all signal names are mapped\n");
log("the the signal name of the primary driver. Using the -nomap option deactivates\n"); log("to the signal name of the primary driver. Using the -nomap option deactivates\n");
log("this behavior.\n"); log("this behavior.\n");
log("\n"); log("\n");
log("The connect command operates in one module only. Either only one module must\n"); log("The connect command operates in one module only. Either only one module must\n");
@ -77,6 +89,8 @@ struct ConnectPass : public Pass {
log("\n"); log("\n");
log("This command does not operate on module with processes.\n"); log("This command does not operate on module with processes.\n");
log("\n"); log("\n");
log("Overriding any bits connected to a module input port will remove the input port.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {