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https://github.com/YosysHQ/yosys
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proc_dff: refactor inference logic
* Instead of an ad hoc mix of optimizations and inferences, this tries to make it more principled by first extracting a set of asynchronous update rules from the process, then optimizing them before lowering them to a concrete flip-flop type, preferring simpler ones
This commit is contained in:
George Rennie
parent
b30211c60a
commit
bd2cdd31af
1 changed files with 375 additions and 222 deletions
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@ -24,25 +24,26 @@
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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#include <algorithm>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
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RTLIL::SigSpec find_any_lvalue(const RTLIL::Process& proc)
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{
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RTLIL::SigSpec lvalue;
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for (auto sync : proc->syncs)
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for (auto &action : sync->actions)
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for (const auto* sync : proc.syncs)
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for (const auto& action : sync->actions)
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if (action.first.size() > 0) {
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lvalue = action.first;
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lvalue.sort_and_unify();
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break;
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}
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for (auto sync : proc->syncs) {
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for (const auto* sync : proc.syncs) {
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RTLIL::SigSpec this_lvalue;
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for (auto &action : sync->actions)
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for (const auto& action : sync->actions)
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this_lvalue.append(action.first);
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this_lvalue.sort_and_unify();
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RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue);
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@ -53,238 +54,390 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
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return lvalue;
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}
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void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
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std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
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{
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// A signal should be set/cleared if there is a load trigger that is enabled
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// such that the load value is 1/0 and it is the highest priority trigger
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RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
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RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
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std::string new_dff_name() {
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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return sstr.str();
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}
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// Reverse iterate through the rules as the first ones are the highest priority
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// so need to be at the top of the mux trees
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for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++)
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class Dff {
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public:
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// Extract the relevant signals from a process that drives sig as a DFF
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Dff(RTLIL::Module& mod, const SigSpec& sig_out, RTLIL::Process& proc) :
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proc{proc}, mod{mod}, sig_in(RTLIL::State::Sz, sig_out.size()), sig_out{sig_out}
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{
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const auto& [sync_value, rule] = *it;
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const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal);
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// We gather sync rules corresponding to always/edge first to check
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// whether they are conflicting before actually updating clk
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const RTLIL::SyncRule* sync_edge = nullptr;
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const RTLIL::SyncRule* sync_always = nullptr;
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bool global_clock = false;
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// If pos_trig is true, we have priority at this point in the tree so
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// set a bit if sync_value has a set bit. Otherwise, defer to the rest
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// of the priority tree
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sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig);
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for (const auto* sync : proc.syncs)
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for (const auto& action : sync->actions) {
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if (action.first.extract(sig_out).empty())
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continue;
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// Same deal with clear bit
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const auto sync_value_inv = mod->Not(NEW_ID, sync_value);
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sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig);
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// Level sensitive assignments (set/reset/aload)
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if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
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RTLIL::SigSpec rstval(RTLIL::State::Sz, sig_out.size());
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sig_out.replace(action.first, action.second, &rstval);
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async_rules.emplace_back(rstval, *sync);
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continue;
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}
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// Edge sensitive assignments (clock)
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if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
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if (sync_edge != NULL && sync_edge != sync)
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log_error("Multiple edge sensitive events found for this signal!\n");
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sig_out.replace(action.first, action.second, &sig_in);
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sync_edge = sync;
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continue;
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}
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// Always assignments
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if (sync->type == RTLIL::SyncType::STa) {
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if (sync_always != NULL && sync_always != sync)
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log_error("Multiple always events found for this signal!\n");
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sig_out.replace(action.first, action.second, &sig_in);
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sync_always = sync;
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continue;
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}
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// Global clock assignments
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if (sync->type == RTLIL::SyncType::STg) {
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sig_out.replace(action.first, action.second, &sig_in);
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global_clock = true;
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continue;
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}
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log_error("Event with any-edge sensitivity found for this signal!\n");
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}
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if (sync_always && (sync_edge || !async_rules.empty()))
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log_error("Mixed always event with edge and/or level sensitive events!\n");
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if (!sync_edge && !global_clock && !sync_always)
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log_error("Missing edge-sensitive event for this signal!\n");
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// Update our internal versions of these signals to track whether things
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// are edge sensitive
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if (sync_edge)
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clk = *sync_edge;
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always = sync_always != nullptr;
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}
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::Cell *cell = mod->addDffsr(sstr.str(), clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity);
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cell->attributes = proc->attributes;
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log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
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cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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}
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void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
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bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
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{
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($aldff));
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cell->attributes = proc->attributes;
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cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
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cell->parameters[ID::ALOAD_POLARITY] = RTLIL::Const(set_polarity, 1);
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cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
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cell->setPort(ID::D, sig_in);
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cell->setPort(ID::Q, sig_out);
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cell->setPort(ID::AD, sig_set);
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cell->setPort(ID::CLK, clk);
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cell->setPort(ID::ALOAD, set);
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log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
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clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
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}
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void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RTLIL::SigSpec sig_out,
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bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
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{
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
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cell->attributes = proc->attributes;
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cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
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if (arst) {
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cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1);
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cell->parameters[ID::ARST_VALUE] = val_rst;
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}
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if (!clk.empty()) {
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cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
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void optimize(ConstEval& ce) {
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optimize_const_eval(ce);
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optimize_same_value(ce);
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optimize_self_assign(ce);
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}
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cell->setPort(ID::D, sig_in);
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cell->setPort(ID::Q, sig_out);
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if (arst)
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cell->setPort(ID::ARST, *arst);
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if (!clk.empty())
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cell->setPort(ID::CLK, clk);
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// Const evaluate async rule values and triggers, and remove those that
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// have triggers that are always false
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void optimize_const_eval(ConstEval& ce) {
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ce.eval(sig_in);
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ce.eval(clk.sig);
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if (!clk.empty())
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log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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else
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log(" created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str());
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if (arst)
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log(" and %s level reset", arst_polarity ? "positive" : "negative");
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log(".\n");
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}
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for (auto& [value, trigger] : async_rules) {
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ce.eval(value);
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ce.eval(trigger.sig);
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}
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void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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{
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while (1)
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{
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RTLIL::SigSpec sig = find_any_lvalue(proc);
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async_rules.erase(
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std::remove_if(async_rules.begin(), async_rules.end(),
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[](const auto& rule) { return rule.trigger.is_never_triggered(); }
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),
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async_rules.end()
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);
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}
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if (sig.size() == 0)
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// Combine adjacent async rules that assign the same value into one rule
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// with a disjunction of triggers. The resulting trigger is optimized by
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// constant evaluation.
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void optimize_same_value(ConstEval& ce) {
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for (size_t i = 0; i + 1 < async_rules.size();) {
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if (async_rules[i].value != async_rules[i + 1].value) {
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i++;
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continue;
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}
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// i and i + 1 assign the same value so can be merged by taking
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// the disjunction of triggers and deleting the second
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async_rules[i].trigger = mod.ReduceOr(
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NEW_ID,
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SigSpec{
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async_rules[i].trigger.positive_trigger(mod),
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async_rules[i + 1].trigger.positive_trigger(mod)
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}
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);
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async_rules.erase(async_rules.begin() + i + 1);
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ce.eval(async_rules[i].trigger.sig);
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}
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}
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// If the lowest priority async rule assigns the output value to itself,
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// remove the rule and fold this into the input signal.
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void optimize_self_assign(ConstEval& ce) {
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SigSpec sig_out_mapped = sig_out;
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ce.assign_map.apply(sig_out_mapped);
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size_t new_size = async_rules.size();
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for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++) {
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const auto& [value, trigger] = *it;
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if (value != sig_out_mapped)
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break;
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if (!trigger.inverted)
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sig_in = mod.Mux(NEW_ID, sig_in, value, trigger.sig);
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else
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sig_in = mod.Mux(NEW_ID, value, sig_in, trigger.sig);
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ce.eval(sig_in);
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new_size--;
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}
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async_rules.resize(new_size);
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}
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void generate() {
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// Progressively attempt more complex formulations, preferring the
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// simpler ones. These rules should be able to cover all representable
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// DFF patterns.
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if (try_generate_always())
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return;
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if (try_generate_dff())
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return;
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if (try_generate_single_async_dff())
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return;
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if (try_generate_dffsr())
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return;
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log_error("unable to match a dff type to this signal's rules.\n");
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}
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// Generates a connection if this dff is an always connection
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// Returns true if successful
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bool try_generate_always() {
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if (!always)
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return false;
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log_assert(async_rules.empty());
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log_assert(clk.empty());
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log(" created direct connection (no actual register cell created).\n");
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mod.connect(sig_out, sig_in);
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return true;
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}
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// Generates a $dff if this dff has no async rules and a clock of a $ff
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// if this dff has no async rules and is globally clocked
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// Returns true if succesful
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bool try_generate_dff() {
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if (always || !async_rules.empty())
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return false;
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RTLIL::Cell* cell;
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const char* edge;
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if (clk.empty()) {
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edge = "global";
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cell = mod.addFf(new_dff_name(), sig_in, sig_out);
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} else {
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edge = clk.polarity_str();
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cell = mod.addDff(
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/* name */ new_dff_name(),
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/* sig_clk */ clk.sig,
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/* sig_d */ sig_in,
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/* sig_q */ sig_out,
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/* clk_polarity */ clk.polarity()
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);
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}
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cell->attributes = proc.attributes;
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log(" created %s cell `%s' with %s edge clock.", cell->type.c_str(), cell->name.c_str(), edge);
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return true;
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}
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// Generates an $adff or $aldff if this dff has a single async rule that
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// is constant or non-constant respectively
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// Returns true if successful
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bool try_generate_single_async_dff() {
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if (!explicitly_clocked() || async_rules.size() != 1)
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return false;
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const auto& aload = async_rules.front();
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const bool is_const = aload.value.is_fully_const();
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RTLIL::Cell* cell;
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if (is_const) {
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cell = mod.addAdff(
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/* name */ new_dff_name(),
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/* sig_clk */ clk.sig,
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/* sig_arst */ aload.trigger.sig,
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/* sig_d */ sig_in,
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/* sig_q */ sig_out,
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/* arst_value */ aload.value.as_const(),
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/* clk_polarity */ clk.polarity(),
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/* arst_polarity */ aload.trigger.polarity()
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);
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} else {
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log_warning("Async reset value `%s' is not constant!\n", log_signal(aload.value));
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cell = mod.addAldff(
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/* name */ new_dff_name(),
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/* sig_clk */ clk.sig,
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/* sig_aload */ aload.trigger.sig,
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/* sig_d */ sig_in,
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/* sig_q */ sig_out,
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/* sig_ad */ aload.value,
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/* clk_polarity */ clk.polarity(),
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/* aload_polarity */ aload.trigger.polarity()
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);
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}
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cell->attributes = proc.attributes;
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log(
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" created %s cell `%s' with %s edge clock and %s level %sconst reset.\n",
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cell->type.c_str(), cell->name.c_str(), clk.polarity_str(), aload.trigger.polarity_str(),
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is_const ? "" : "non-"
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);
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return true;
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}
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// Generates a $dffsr cell from a complex set of async rules that are converted
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// into driving conditions for set and reset signals
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// Returns true if successful
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bool try_generate_dffsr() {
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if (!explicitly_clocked())
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return false;
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// A signal should be set/cleared if there is a load trigger that is enabled
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// such that the load value is 1/0 and it is the highest priority trigger
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RTLIL::SigSpec sig_set(0, size()), sig_clr(0, size());
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// Reverse iterate through the rules as the first ones are the highest priority
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// so need to be at the top of the mux trees
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for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++) {
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const auto& [sync_value, trigger] = *it;
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const auto pos_trig = trigger.positive_trigger(mod);
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// If pos_trig is true, we have priority at this point in the tree so
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// set a bit if value has a set bit. Otherwise, defer to the rest
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// of the priority tree
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sig_set = mod.Mux(NEW_ID, sig_set, sync_value, pos_trig);
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// Same deal with clear bit
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const auto sync_value_inv = mod.Not(NEW_ID, sync_value);
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sig_clr = mod.Mux(NEW_ID, sig_clr, sync_value_inv, pos_trig);
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}
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auto* cell = mod.addDffsr(
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/* name */ new_dff_name(),
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/* sig_clk */ clk.sig,
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/* sig_set */ sig_set,
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/* sig_clr */ sig_clr,
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/* sig_d */ sig_in,
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/* sig_q */ sig_out,
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/* clk_polarity */ clk.polarity()
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);
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cell->attributes = proc.attributes;
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log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
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cell->type.c_str(), cell->name.c_str(), clk.polarity_str());
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return true;
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}
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bool empty() const { return sig_out.empty(); }
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size_t size() const { return sig_out.size(); }
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const SigSpec& output() const { return sig_out; }
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// True if there is an explicit clock signal, false if driven by an always
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// or global clock
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||||
bool explicitly_clocked() const { return !always && !clk.empty(); }
|
||||
|
||||
private:
|
||||
RTLIL::Process& proc;
|
||||
RTLIL::Module& mod;
|
||||
|
||||
// A clock or reset trigger that is active when sig goes high (low) when
|
||||
// inverted is false (true)
|
||||
struct TriggerSig {
|
||||
SigSpec sig;
|
||||
bool inverted = false;
|
||||
|
||||
TriggerSig() = default;
|
||||
TriggerSig(const RTLIL::SyncRule& sync) : sig{sync.signal},
|
||||
inverted{sync.type == RTLIL::SyncType::ST0 || sync.type == RTLIL::SyncType::STn} {}
|
||||
|
||||
TriggerSig(const RTLIL::SigSpec& signal) : sig{signal} {}
|
||||
|
||||
bool empty() const { return sig.empty(); }
|
||||
bool polarity() const { return !inverted; }
|
||||
const char* polarity_str() const { return polarity() ? "positive" : "negative"; }
|
||||
|
||||
bool is_never_triggered() const {
|
||||
return inverted ? sig.is_fully_ones() : sig.is_fully_zero();
|
||||
}
|
||||
|
||||
SigSpec positive_trigger(RTLIL::Module& mod) const {
|
||||
if (!inverted)
|
||||
return sig;
|
||||
return mod.Not(NEW_ID, sig);
|
||||
}
|
||||
};
|
||||
|
||||
// An update rule to update sig_q to value when trigger is triggered
|
||||
struct AsyncRule {
|
||||
SigSpec value;
|
||||
TriggerSig trigger;
|
||||
|
||||
AsyncRule() = default;
|
||||
AsyncRule(const SigSpec& value, const RTLIL::SyncRule& sync) : value{value}, trigger{sync} {}
|
||||
};
|
||||
|
||||
// The d input (used when no async rules apply) and q output
|
||||
SigSpec sig_in, sig_out;
|
||||
|
||||
// A priority ordered list of asynchronous rules used for set/reset/aload.
|
||||
// A rule that comes earlier in this vector has higher priority than a later
|
||||
// one (if both of their trigger conditions are met the higher priority
|
||||
// value is taken)
|
||||
std::vector<AsyncRule> async_rules;
|
||||
|
||||
// The clock signal with its polarity. If clk is empty, the DFF is driven
|
||||
// by a global clock (and should have no async rules)
|
||||
TriggerSig clk;
|
||||
|
||||
// If this is true, this isn't really a DFF but instead an always assignment
|
||||
// that can be made with a connection. clk and async_rules should be empty
|
||||
// in this case
|
||||
bool always = false;
|
||||
};
|
||||
|
||||
void proc_dff(RTLIL::Module& mod, RTLIL::Process& proc, ConstEval &ce) {
|
||||
while (1) {
|
||||
// Find a new signal assigned by this process
|
||||
const auto sig = find_any_lvalue(proc);
|
||||
if (sig.empty())
|
||||
break;
|
||||
|
||||
log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
|
||||
mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
|
||||
mod.name.c_str(), log_signal(sig), mod.name.c_str(), proc.name.c_str());
|
||||
|
||||
RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
|
||||
RTLIL::SyncRule *sync_edge = NULL;
|
||||
RTLIL::SyncRule *sync_always = NULL;
|
||||
bool global_clock = false;
|
||||
Dff dff{mod, sig, proc};
|
||||
dff.optimize(ce);
|
||||
dff.generate();
|
||||
|
||||
// A priority ordered set of rules, pairing the value to be assigned for
|
||||
// that rule to the rule
|
||||
std::vector<std::pair<RTLIL::SigSpec, RTLIL::SyncRule*>> async_rules;
|
||||
|
||||
// Needed when the async rules are collapsed into one as async_rules
|
||||
// works with pointers to SyncRule
|
||||
RTLIL::SyncRule single_async_rule;
|
||||
|
||||
for (auto sync : proc->syncs)
|
||||
for (auto &action : sync->actions)
|
||||
{
|
||||
if (action.first.extract(sig).size() == 0)
|
||||
continue;
|
||||
|
||||
if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
|
||||
RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
|
||||
sig.replace(action.first, action.second, &rstval);
|
||||
async_rules.emplace_back(rstval, sync);
|
||||
}
|
||||
else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
|
||||
if (sync_edge != NULL && sync_edge != sync)
|
||||
log_error("Multiple edge sensitive events found for this signal!\n");
|
||||
sig.replace(action.first, action.second, &insig);
|
||||
sync_edge = sync;
|
||||
}
|
||||
else if (sync->type == RTLIL::SyncType::STa) {
|
||||
if (sync_always != NULL && sync_always != sync)
|
||||
log_error("Multiple always events found for this signal!\n");
|
||||
sig.replace(action.first, action.second, &insig);
|
||||
sync_always = sync;
|
||||
}
|
||||
else if (sync->type == RTLIL::SyncType::STg) {
|
||||
sig.replace(action.first, action.second, &insig);
|
||||
global_clock = true;
|
||||
}
|
||||
else {
|
||||
log_error("Event with any-edge sensitivity found for this signal!\n");
|
||||
}
|
||||
|
||||
action.first.remove2(sig, &action.second);
|
||||
}
|
||||
|
||||
// If all async rules assign the same value, priority ordering between
|
||||
// them doesn't matter so they can be collapsed together into one rule
|
||||
// with the disjunction of triggers
|
||||
if (!async_rules.empty() &&
|
||||
std::all_of(async_rules.begin(), async_rules.end(), [&](auto& p) {
|
||||
return p.first == async_rules.front().first;
|
||||
}))
|
||||
{
|
||||
const auto rstval = async_rules.front().first;
|
||||
|
||||
// The trigger is the disjunction of existing triggers
|
||||
// (with appropriate negation)
|
||||
RTLIL::SigSpec triggers;
|
||||
for (const auto &[_, it] : async_rules)
|
||||
triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal));
|
||||
|
||||
// Put this into the dummy sync rule so it can be treated the same
|
||||
// as ones coming from the module
|
||||
single_async_rule.type = RTLIL::SyncType::ST1;
|
||||
single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
|
||||
single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval));
|
||||
|
||||
// Replace existing rules with this new rule
|
||||
async_rules.clear();
|
||||
async_rules.emplace_back(rstval, &single_async_rule);
|
||||
}
|
||||
|
||||
SigSpec sig_q = sig;
|
||||
ce.assign_map.apply(insig);
|
||||
ce.assign_map.apply(sig);
|
||||
|
||||
// If the reset value assigns the reg to itself, add this as part of
|
||||
// the input signal and delete the rule
|
||||
if (async_rules.size() == 1 && async_rules.front().first == sig) {
|
||||
const auto& [_, rule] = async_rules.front();
|
||||
if (rule->type == RTLIL::SyncType::ST1)
|
||||
insig = mod->Mux(NEW_ID, insig, sig, rule->signal);
|
||||
else
|
||||
insig = mod->Mux(NEW_ID, sig, insig, rule->signal);
|
||||
|
||||
async_rules.clear();
|
||||
}
|
||||
|
||||
if (sync_always) {
|
||||
if (sync_edge || !async_rules.empty())
|
||||
log_error("Mixed always event with edge and/or level sensitive events!\n");
|
||||
log(" created direct connection (no actual register cell created).\n");
|
||||
mod->connect(RTLIL::SigSig(sig, insig));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!sync_edge && !global_clock)
|
||||
log_error("Missing edge-sensitive event for this signal!\n");
|
||||
|
||||
// More than one reset value so we derive a dffsr formulation
|
||||
if (async_rules.size() > 1)
|
||||
{
|
||||
log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
|
||||
gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
|
||||
continue;
|
||||
}
|
||||
|
||||
// If there is a reset condition in the async rules, use it
|
||||
SigSpec rstval = async_rules.empty() ? RTLIL::SigSpec(RTLIL::State::Sz, sig.size()) : async_rules.front().first;
|
||||
RTLIL::SyncRule* sync_level = async_rules.empty() ? nullptr : async_rules.front().second;
|
||||
ce.assign_map.apply(rstval);
|
||||
|
||||
if (!rstval.is_fully_const() && !ce.eval(rstval))
|
||||
{
|
||||
log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
|
||||
gen_aldff(mod, insig, rstval, sig_q,
|
||||
sync_edge->type == RTLIL::SyncType::STp,
|
||||
sync_level && sync_level->type == RTLIL::SyncType::ST1,
|
||||
sync_edge->signal, sync_level->signal, proc);
|
||||
continue;
|
||||
}
|
||||
|
||||
gen_dff(mod, insig, rstval.as_const(), sig_q,
|
||||
sync_edge && sync_edge->type == RTLIL::SyncType::STp,
|
||||
sync_level && sync_level->type == RTLIL::SyncType::ST1,
|
||||
sync_edge ? sync_edge->signal : SigSpec(),
|
||||
sync_level ? &sync_level->signal : NULL, proc);
|
||||
// Now that we are done with the signal remove it from the process
|
||||
// We must do this after optimizing the dff as to emit an optimal dff
|
||||
// type we might not actually use all bits of sig in this iteration
|
||||
for (auto* sync : proc.syncs)
|
||||
for (auto& action : sync->actions)
|
||||
action.first.remove2(dff.output(), &action.second);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -311,7 +464,7 @@ struct ProcDffPass : public Pass {
|
|||
ConstEval ce(mod);
|
||||
for (auto &proc_it : mod->processes)
|
||||
if (design->selected(mod, proc_it.second))
|
||||
proc_dff(mod, proc_it.second, ce);
|
||||
proc_dff(*mod, *proc_it.second, ce);
|
||||
}
|
||||
}
|
||||
} ProcDffPass;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue