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Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
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5 changed files with 61 additions and 28 deletions
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@ -348,7 +348,7 @@ namespace AST
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RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail) override;
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RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override;
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std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet = false);
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void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
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void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override;
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RTLIL::Module *clone() const override;
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void loadconfig() const;
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};
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@ -395,6 +395,18 @@ namespace AST_INTERNAL
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extern dict<std::string, pool<int>> current_memwr_visible;
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struct LookaheadRewriter;
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struct ProcessGenerator;
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// Create and add a new AstModule from new_ast, then use it to replace
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// old_module in design, renaming old_module to move it out of the way.
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// Return the new module.
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//
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// If original_ast is not null, it will be used as the AST node for the
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// new module. Otherwise, new_ast will be used.
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RTLIL::Module *
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process_and_replace_module(RTLIL::Design *design,
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RTLIL::Module *old_module,
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AST::AstNode *new_ast,
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AST::AstNode *original_ast = nullptr);
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}
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YOSYS_NAMESPACE_END
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