3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00

Merge pull request #5062 from YosysHQ/emil/fix-dangling-wiretype

simplify: fix struct wiretype attr memory leak
This commit is contained in:
KrystalDelusion 2025-04-26 11:04:38 +12:00 committed by GitHub
commit bcc4e86c9d
No known key found for this signature in database
GPG key ID: B5690EEEBB952194

View file

@ -1919,6 +1919,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) {
// replace instance with wire representing the packed structure // replace instance with wire representing the packed structure
newNode = make_packed_struct(template_node, str, attributes); newNode = make_packed_struct(template_node, str, attributes);
if (newNode->attributes.count(ID::wiretype))
delete newNode->attributes[ID::wiretype];
newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
// add original input/output attribute to resolved wire // add original input/output attribute to resolved wire
newNode->is_input = this->is_input; newNode->is_input = this->is_input;