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Merge branch 'master' into xaig

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Eddie Hung 2019-04-08 16:31:59 -07:00
commit bca3cf6843
115 changed files with 5852 additions and 720 deletions
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1
tests/asicworld/xfirrtl
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@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v combinational loop
code_hdl_models_dff_async_reset.v $adff
code_hdl_models_tff_async_reset.v $adff
code_hdl_models_uart.v $adff
code_specman_switch_fabric.v subfield assignment (bits() <= ...)
code_tidbits_asyn_reset.v $adff
code_tidbits_reg_seq_example.v $adff
code_verilog_tutorial_always_example.v empty module

2
tests/liberty/.gitignore vendored Normal file
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@ -0,0 +1,2 @@
*.log
test.ys

81
tests/liberty/busdef.lib Normal file
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@ -0,0 +1,81 @@
/********************************************/
/* */
/* Supergate cell library for Bench marking */
/* */
/* Symbiotic EDA GmbH / Moseley Instruments */
/* Niels A. Moseley */
/* */
/* Process: none */
/* */
/* Date : 02-11-2018 */
/* Version: 1.0 */
/* */
/********************************************/
library(supergate) {
technology (cmos);
revision : 1.0;
time_unit : "1ps";
pulling_resistance_unit : "1kohm";
voltage_unit : "1V";
current_unit : "1uA";
capacitive_load_unit(1,ff);
default_inout_pin_cap : 7.0;
default_input_pin_cap : 7.0;
default_output_pin_cap : 0.0;
default_fanout_load : 1.0;
default_wire_load_capacitance : 0.1;
default_wire_load_resistance : 1.0e-3;
default_wire_load_area : 0.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.2;
delay_model : generic_cmos;
type( IO_bus_3_to_0 ) {
base_type : array ;
data_type : bit ;
bit_width : 4;
bit_from : 3 ;
bit_to : 0 ;
downto : true ;
}
cell (SRAM) {
area : 1 ;
memory() {
type : ram;
address_width : 4;
word_width : 4;
}
pin(CE1) {
direction : input;
capacitance : 0.021;
max_transition : 1.024;
switch_pin : true;
}
bus(I1) {
bus_type : IO_bus_3_to_0 ;
direction : input;
pin (I1[3:0]) {
timing() {
related_pin : "CE1" ;
timing_type : setup_rising ;
rise_constraint (scalar) {
values("0.0507786");
}
fall_constraint (scalar) {
values("0.0507786");
}
}
}
}
}
} /* end */

359
tests/liberty/normal.lib Normal file
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@ -0,0 +1,359 @@
/********************************************/
/* */
/* Supergate cell library for Bench marking */
/* */
/* Symbiotic EDA GmbH / Moseley Instruments */
/* Niels A. Moseley */
/* */
/* Process: none */
/* */
/* Date : 02-11-2018 */
/* Version: 1.0 */
/* */
/********************************************/
library(supergate) {
technology (cmos);
revision : 1.0;
time_unit : "1ps";
pulling_resistance_unit : "1kohm";
voltage_unit : "1V";
current_unit : "1uA";
capacitive_load_unit(1,ff);
default_inout_pin_cap : 7.0;
default_input_pin_cap : 7.0;
default_output_pin_cap : 0.0;
default_fanout_load : 1.0;
default_wire_load_capacitance : 0.1;
default_wire_load_resistance : 1.0e-3;
default_wire_load_area : 0.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.2;
delay_model : generic_cmos;
/* Inverter */
cell (inv) {
area : 1;
pin(A) {
direction : input;
}
pin(Y) {
direction : output;
function : "A'";
}
}
/* tri-state inverter */
cell (tri_inv) {
area : 4;
pin(A) {
direction : input;
}
pin(S) {
direction : input;
}
pin(Z) {
direction : output;
function : "A'";
three_State : "S'";
}
}
cell (buffer) {
area : 5;
pin(A) {
direction : input;
}
pin(Y) {
direction : output;
function : "A";
}
}
/* 2-input NAND gate */
cell (nand2) {
area : 3;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(Y) {
direction: output;
function : "(A * B)'";
}
}
/* 2-input NOR gate */
cell (nor2) {
area : 3;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(Y) {
direction: output;
function : "(A + B)'";
}
}
/* 2-input XOR */
cell (xor2) {
area : 6;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(Y) {
direction: output;
function : "(A *B') + (A' * B)";
}
}
/* 2-input inverting MUX */
cell (imux2) {
area : 5;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(S) {
direction : input;
}
pin(Y) {
direction: output;
function : "( (A * S) + (B * S') )'";
}
}
/* D-type flip-flop with asynchronous reset and preset */
cell (dff) {
area : 6;
ff("IQ", "IQN") {
next_state : "D";
clocked_on : "CLK";
clear : "RESET";
preset : "PRESET";
clear_preset_var1 : L;
clear_preset_var2 : L;
}
pin(D) {
direction : input;
}
pin(CLK) {
direction : input;
}
pin(RESET) {
direction : input;
}
pin(PRESET) {
direction : input;
}
pin(Q) {
direction: output;
function : "IQ";
timing() {
timing_type : rising_edge;
intrinsic_rise : 65;
intrinsic_fall : 65;
rise_resistance : 0;
fall_resistance : 0;
related_pin : "CLK";
}
timing () {
timing_type : clear;
timing_sense : positive_unate;
intrinsic_fall : 75;
related_pin : "RESET";
}
timing () {
timing_type : preset;
timing_sense : negative_unate;
intrinsic_rise : 75;
related_pin : "PRESET";
}
}
pin(QN) {
direction: output;
function : "IQN";
timing() {
timing_type : rising_edge;
intrinsic_rise : 65;
intrinsic_fall : 65;
rise_resistance : 0;
fall_resistance : 0;
related_pin : "CLK";
}
timing () {
timing_type : preset;
timing_sense : negative_unate;
intrinsic_rise : 75;
related_pin : "RESET";
}
timing () {
timing_type : clear;
timing_sense : positive_unate;
intrinsic_fall : 75;
related_pin : "PRESET";
}
}
}
/* Latch */
cell(latch) {
area : 5;
latch ("IQ","IQN") {
enable : "G";
data_in : "D";
}
pin(D) {
direction : input;
}
pin(G) {
direction : input;
}
pin(Q) {
direction : output;
function : "IQ";
internal_node : "Q";
timing() {
timing_type : rising_edge;
intrinsic_rise : 65;
intrinsic_fall : 65;
rise_resistance : 0;
fall_resistance : 0;
related_pin : "G";
}
timing() {
timing_sense : positive_unate;
intrinsic_rise : 65;
intrinsic_fall : 65;
rise_resistance : 0;
fall_resistance : 0;
related_pin : "D";
}
}
pin(QN) {
direction : output;
function : "IQN";
internal_node : "QN";
timing() {
timing_type : rising_edge;
intrinsic_rise : 65;
intrinsic_fall : 65;
rise_resistance : 0;
fall_resistance : 0;
related_pin : "G";
}
timing() {
timing_sense : negative_unate;
intrinsic_rise : 65;
intrinsic_fall : 65;
rise_resistance : 0;
fall_resistance : 0;
related_pin : "D";
}
}
}
/* 3 input AND-OR-INVERT gate */
cell (aoi211) {
area : 3;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(C) {
direction : input;
}
pin(Y) {
direction: output;
function : "((A * B) + C)'";
}
}
/* 3 input OR-AND-INVERT gate */
cell (oai211) {
area : 3;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(C) {
direction : input;
}
pin(Y) {
direction: output;
function : "((A + B) * C)'";
}
}
/* half adder */
cell (halfadder) {
area : 5;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(C) {
direction : output;
function : "(A * B)";
}
pin(Y) {
direction: output;
function : "(A *B') + (A' * B)";
}
}
/* full adder */
cell (fulladder) {
area : 8;
pin(A) {
direction : input;
}
pin(B) {
direction : input;
}
pin(CI) {
direction : input;
}
pin(CO) {
direction : output;
function : "(((A * B)+(B * CI))+(CI * A))";
}
pin(Y) {
direction: output;
function : "((A^B)^CI)";
}
}
} /* end */

48
tests/liberty/processdefs.lib Normal file
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@ -0,0 +1,48 @@
/********************************************/
/* */
/* Supergate cell library for Bench marking */
/* */
/* Symbiotic EDA GmbH / Moseley Instruments */
/* Niels A. Moseley */
/* */
/* Process: none */
/* */
/* Date : 25-03-2019 */
/* Version: 1.0 */
/* */
/********************************************/
library(processdefs) {
technology (cmos);
revision : 1.0;
time_unit : "1ps";
pulling_resistance_unit : "1kohm";
voltage_unit : "1V";
current_unit : "1uA";
capacitive_load_unit(1,ff);
default_inout_pin_cap : 7.0;
default_input_pin_cap : 7.0;
default_output_pin_cap : 0.0;
default_fanout_load : 1.0;
default_wire_load_capacitance : 0.1;
default_wire_load_resistance : 1.0e-3;
default_wire_load_area : 0.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.2;
delay_model : generic_cmos;
define_cell_area(bond_pads,pad_slots)
input_voltage(cmos) {
vil : 0.3 * VDD ;
vih : 0.7 * VDD ;
vimin : -0.5 ;
vimax : VDD + 0.5 ;
}
}

10
tests/liberty/run-test.sh Executable file
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@ -0,0 +1,10 @@
#!/bin/bash
set -e
for x in *.lib; do
echo "Running $x.."
echo "read_verilog small.v" > test.ys
echo "synth -top small" >> test.ys
echo "dfflibmap -liberty ${x}" >> test.ys
../../yosys -ql ${x%.lib}.log -s test.ys
done

48
tests/liberty/semicolextra.lib Normal file
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@ -0,0 +1,48 @@
/*
Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/
fall_constraint (SETUP_HOLD) formatting.
*/
library(supergate) {
technology (cmos);
revision : 1.0;
cell (DFF) {
cell_footprint : dff;
area : 50;
pin(D) {
direction : input;
capacitance : 0.002;
timing() {
related_pin : "CK";
timing_type : setup_rising;
fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \
"0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
"0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
"0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
"1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); };
}
}
pin(CK) {
direction : input;
clock : true;
capacitance : 0.00290;
}
ff(IQ,IQN) {
clocked_on : "CK";
next_state : "D";
}
pin(Q) {
direction : output;
capacitance : 0.003;
max_capacitance : 0.3;
}
cell_leakage_power : 0.3;
}
}

72
tests/liberty/semicolmissing.lib Normal file
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@ -0,0 +1,72 @@
/********************************************/
/* */
/* Supergate cell library for Bench marking */
/* */
/* Symbiotic EDA GmbH / Moseley Instruments */
/* Niels A. Moseley */
/* */
/* Process: none */
/* */
/* Date : 24-03-2019 */
/* Version: 1.0 */
/* Version: 1.1 - Removed semicolons in */
/* full adder */
/* */
/********************************************/
/*
semi colon is missing in full-adder specification
some TSMC liberty files are formatted this way..
*/
library(supergate) {
technology (cmos);
revision : 1.0;
time_unit : "1ps";
pulling_resistance_unit : "1kohm";
voltage_unit : "1V";
current_unit : "1uA";
capacitive_load_unit(1,ff);
default_inout_pin_cap : 7.0;
default_input_pin_cap : 7.0;
default_output_pin_cap : 0.0;
default_fanout_load : 1.0;
default_wire_load_capacitance : 0.1;
default_wire_load_resistance : 1.0e-3;
default_wire_load_area : 0.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.2;
delay_model : generic_cmos;
/* full adder */
cell (fulladder) {
area : 8
pin(A) {
direction : input
}
pin(B) {
direction : input
}
pin(CI) {
direction : input
}
pin(CO) {
direction : output
function : "(((A * B)+(B * CI))+(CI * A))"
}
pin(Y) {
direction: output
function : "((A^B)^CI)"
}
}
} /* end */

16
tests/liberty/small.v Normal file
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@ -0,0 +1,16 @@
/** small, meaningless design to test loading of liberty files */
module small
(
input clk,
output reg[7:0] count
);
initial count = 0;
always @ (posedge clk)
begin
count <= count + 1'b1;
end
endmodule

58
tests/simple/generate.v
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@ -90,5 +90,61 @@ generate
endcase
end
endgenerate
endmodule
// ------------------------------------------
module gen_test4(a, b);
input [3:0] a;
output [3:0] b;
genvar i;
generate
for (i=0; i < 3; i=i+1) begin : foo
localparam PREV = i - 1;
wire temp;
if (i == 0)
assign temp = a[0];
else
assign temp = foo[PREV].temp & a[i];
assign b[i] = temp;
end
endgenerate
endmodule
// ------------------------------------------
module gen_test5(input_bits, out);
parameter WIDTH = 256;
parameter CHUNK = 4;
input [WIDTH-1:0] input_bits;
output out;
genvar step, i, j;
generate
for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
localparam PREV = step / CHUNK;
localparam DIM = WIDTH / step;
for (i = 0; i < DIM; i = i + 1) begin : outer
localparam LAST_START = i * CHUNK;
for (j = 0; j < CHUNK; j = j + 1) begin : inner
wire temp;
if (step == 1)
assign temp = input_bits[i];
else if (j == 0)
assign temp = steps[PREV].outer[LAST_START].val;
else
assign temp
= steps[step].outer[i].inner[j-1].temp
& steps[PREV].outer[LAST_START + j].val;
end
wire val;
assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
end
end
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule

19
tests/simple/task_func.v
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@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
assign out3 = test3(in);
assign out4 = test4(in);
endmodule
// -------------------------------------------------------------------
// https://github.com/YosysHQ/yosys/issues/857
module task_func_test05(data_in,data_out,clk);
output reg data_out;
input data_in;
input clk;
task myTask;
output out;
input in;
out = in;
endtask
always @(posedge clk) begin
myTask(data_out,data_in);
end
endmodule

2
tests/simple/xfirrtl
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@ -1,6 +1,7 @@
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
arraycells.v inst id[0] of
dff_different_styles.v
dff_init.v Initial value not supported
generate.v combinational loop
hierdefparam.v inst id[0] of
i2c_master_tests.v $adff
@ -12,7 +13,6 @@ multiplier.v inst id[0] of
muxtree.v drops modules
omsp_dbg_uart.v $adff
operators.v $pow
paramods.v subfield assignment (bits() <= ...)
partsel.v drops modules
process.v drops modules
realexpr.v drops modules

22
tests/sva/extnets.sv Normal file
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@ -0,0 +1,22 @@
module top(input i, output o);
A A();
B B();
assign A.i = i;
assign o = B.o;
always @* assert(o == i);
endmodule
module A;
wire i, y;
`ifdef FAIL
assign B.x = i;
`else
assign B.x = !i;
`endif
assign y = !B.y;
endmodule
module B;
wire x, y, o;
assign y = x, o = A.y;
endmodule

6
tests/tools/autotest.sh
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@ -8,7 +8,7 @@ verbose=false
keeprunning=false
makejmode=false
frontend="verilog"
backend_opts="-noattr -noexpr"
backend_opts="-noattr -noexpr -siminit"
autotb_opts=""
include_opts=""
xinclude_opts=""
@ -49,7 +49,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
r)
backend_opts="$backend_opts -norename" ;;
e)
backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;;
backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
f)
frontend="$OPTARG" ;;
s)
@ -181,7 +181,7 @@ do
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v -X verilog
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
fi
fi