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Merge a4d23c0847
into 5aa9bfbf7d
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commit
bca0f8b84f
12 changed files with 122 additions and 9 deletions
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@ -1803,6 +1803,16 @@ namespace RTLIL_BACKEND {
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void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire);
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}
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struct BoolStruct {
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private:
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bool val;
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public:
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BoolStruct(bool v) : val(v) {}
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operator bool() const {
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return val;
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}
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};
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struct RTLIL::Wire : public RTLIL::NamedObject
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{
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Hasher::hash_t hashidx_;
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@ -1827,7 +1837,16 @@ public:
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RTLIL::Module *module;
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int width, start_offset, port_id;
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bool port_input, port_output, upto, is_signed;
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bool port_input, port_output, is_signed;
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// These are actually just total aliases, relying on
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// common initial sequences of records to avoid UB.
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// This is a retrofit and we don't know if we ensure
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// only the active member is accessed
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union {
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BoolStruct upto; // if width >= 1
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// "single bit vector" vs scalar
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BoolStruct sbvector; // if width == 1
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};
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RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
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RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
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