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Use buf instead of pos

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This commit is contained in:
Alain Dargelas 2025-03-05 09:40:26 -08:00
parent 9f36d9dea9
commit bc05f4fead
1 changed files with 1 additions and 1 deletions
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2
passes/silimate/annotate_cell_fanout.cc
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@ -347,7 +347,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
for (int i = 0; i < num_buffers; ++i) { for (int i = 0; i < num_buffers; ++i) {
std::string wireName = generateSigSpecName(module, sigToBuffer, true, "_wbuf" + std::to_string(index_buffer)).c_str(); std::string wireName = generateSigSpecName(module, sigToBuffer, true, "_wbuf" + std::to_string(index_buffer)).c_str();
std::string cellName = generateSigSpecName(module, sigToBuffer, true, "_fbuf" + std::to_string(index_buffer), true).c_str(); std::string cellName = generateSigSpecName(module, sigToBuffer, true, "_fbuf" + std::to_string(index_buffer), true).c_str();
RTLIL::Cell *buffer = module->addCell(cellName, ID($pos)); RTLIL::Cell *buffer = module->addCell(cellName, ID($buf));
bufferActualFanout[buffer] = 0; bufferActualFanout[buffer] = 0;
RTLIL::SigSpec buffer_output = module->addWire(wireName, chunk.size()); RTLIL::SigSpec buffer_output = module->addWire(wireName, chunk.size());
buffer->setPort(ID(A), chunk); buffer->setPort(ID(A), chunk);