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genrtlil: improve name conflict error messaging

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This commit is contained in:
Zachary Snow 2021-02-26 18:08:23 -05:00
parent dcd9f0af23
commit bbff844acd
7 changed files with 93 additions and 12 deletions
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7
tests/verilog/conflict_memory_wire.ys Normal file
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@ -0,0 +1,7 @@
logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1
read_verilog <<EOT
module top;
reg [2:0] x;
reg [2:0] x [0:0];
endmodule
EOT