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genrtlil: improve name conflict error messaging

This commit is contained in:
Zachary Snow 2021-02-26 18:08:23 -05:00
parent dcd9f0af23
commit bbff844acd
7 changed files with 93 additions and 12 deletions

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@ -0,0 +1,8 @@
logger -expect error "Cannot add procedural assertion `\\x' because a signal with the same name was already created" 1
read_verilog -sv <<EOT
module top;
wire x, y;
always @*
x: assert(y == 1);
endmodule
EOT

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logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1
read_verilog <<EOT
module mod;
endmodule
module top;
reg [2:0] x [0:0];
mod x();
endmodule
EOT

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logger -expect error "Cannot add interface port `\\i' because a signal with the same name was already created" 1
read_verilog -sv <<EOT
interface intf;
logic x;
assign x = 1;
modport m(input x);
endinterface
module mod(intf.m i);
wire x;
assign x = i.x;
wire i;
endmodule
module top;
intf i();
mod m(i);
endmodule
EOT

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@ -0,0 +1,7 @@
logger -expect error "Cannot add memory `\\x' because a signal with the same name was already created" 1
read_verilog <<EOT
module top;
reg [2:0] x;
reg [2:0] x [0:0];
endmodule
EOT

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@ -0,0 +1,8 @@
logger -expect error "Cannot add pwire `\\x' because a signal with the same name was already created" 1
read_verilog -pwires <<EOT
module top;
wire x;
assign x = 1;
localparam x = 2;
endmodule
EOT

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@ -0,0 +1,7 @@
logger -expect error "Cannot add signal `\\x' because a memory with the same name was already created" 1
read_verilog <<EOT
module top;
reg [2:0] x [0:0];
reg [2:0] x;
endmodule
EOT