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	Progress in memory_bram
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					 5 changed files with 18 additions and 16 deletions
				
			
		
							
								
								
									
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								Makefile
									
										
									
									
									
								
							
							
						
						
									
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			@ -264,6 +264,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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	+cd tests/fsm && bash run-test.sh
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	+cd tests/techmap && bash run-test.sh
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	+cd tests/memories && bash run-test.sh
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	+cd tests/bram && bash run-test.sh
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	+cd tests/various && bash run-test.sh
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	+cd tests/sat && bash run-test.sh
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	@echo ""
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			@ -306,10 +306,10 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
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			SigBit last_en_bit = State::S1;
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			for (int i = 0; i < mem_width; i++) {
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				if (pi.enable && i % (bram.dbits / pi.enable) == 0) {
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					last_en_bit = wr_en[i];
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					last_en_bit = wr_en[i + cell_port_i*mem_width];
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					sig_en.append(last_en_bit);
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				}
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				if (last_en_bit != wr_en[i]) {
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				if (last_en_bit != wr_en[i + cell_port_i*mem_width]) {
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					log("      Bram port %c%d has incompatible enable structure.\n", pi.group + 'A', pi.index + 1);
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					goto skip_bram_wport;
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				}
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			@ -328,6 +328,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
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			pi.sig_addr = wr_addr.extract(cell_port_i*mem_abits, mem_abits);
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			pi.sig_data = wr_data.extract(cell_port_i*mem_width, mem_width);
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			bram_port_i++;
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			goto mapped_wr_port;
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		}
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			@ -338,6 +339,7 @@ bool replace_cell(Cell *cell, const rules_t::bram_t &bram, const rules_t::match_
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	int grow_read_ports_cursor = -1;
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	bool try_growing_more_read_ports = false;
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	auto backup_clock_domains = clock_domains;
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	if (0) {
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grow_read_ports:;
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			@ -360,6 +362,7 @@ grow_read_ports:;
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		}
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		try_growing_more_read_ports = false;
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		portinfos.swap(new_portinfos);
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		clock_domains = backup_clock_domains;
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		dup_count++;
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	}
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			@ -448,7 +451,7 @@ grow_read_ports:;
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			string prefix = stringf("%c%d", pi.group + 'A', pi.index + 1);
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			const char *pf = prefix.c_str();
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			if (pi.clocks)
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			if (pi.clocks && (!clocks.count(pi.clocks) || pi.sig_clock.wire))
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				clocks[pi.clocks] = pi.sig_clock;
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			SigSpec addr_ok;
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			@ -15,10 +15,6 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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        dbits  = random.randrange(1, 8)
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        groups = random.randrange(1, 5)
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        # XXX
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        init = 0
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        groups = 2
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        if random.randrange(2):
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            abits = 2 ** random.randrange(1, 4)
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        if random.randrange(2):
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			@ -32,12 +28,10 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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        clkpol = [ random.randrange(4) for i in range(groups) ]
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        # XXX
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        ports  = [ 1 for i in range(groups) ]
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        wrmode = [ 1 for i in range(groups) ]
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        init = 0
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        transp = [ 0 for i in range(groups) ]
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        clocks = [ 1 for i in range(groups) ]
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        clkpol = [ 1 for i in range(groups) ]
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        wrmode[0] = 0
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        for p1 in range(groups):
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            if wrmode[p1] == 0:
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			@ -187,7 +181,7 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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    if debug_mode:
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        print("    $dumpfile(`vcd_file);", file=tb_f)
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        print("    $dumpvars(2, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
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        print("    $dumpvars(0, bram_%02d_%02d_tb);" % (k1, k2), file=tb_f)
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    for p in (tb_clocks + tb_addr + tb_din):
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        if p[-2:] == "EN":
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			@ -205,13 +199,14 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2):
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        if len(tb_clocks):
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            c = random.choice(tb_clocks)
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            print("    %s = !%s;" % (c, c), file=tb_f)
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        print("    #100;", file=tb_f)
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        print("    $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
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                (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
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        for p in tb_din:
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            print("    %s <= %d;" % (p, random.randrange(1048576)), file=tb_f)
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        for p in tb_addr:
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            print("    %s <= %d;" % (p, random.choice(tb_addrlist)), file=tb_f)
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        print("    #1000;", file=tb_f)
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        print("    $display(\"bram_%02d_%02d %3d: %%b %%b %%s\", %s, %s, error ? \"ERROR\" : \"OK\");" %
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                (k1, k2, i, expr_dout, expr_dout_ref), file=tb_f)
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        print("    #900;", file=tb_f)
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    print("  end", file=tb_f)
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    print("endmodule", file=tb_f)
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			@ -5,5 +5,8 @@ set -e
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iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v temp/brams_${1}_ref.v \
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		temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v
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temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt
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if grep -H -C1 ERROR temp/tb_${1}_${2}.txt; then exit 1; fi
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if grep -q ERROR temp/tb_${1}_${2}.txt; then
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	grep -HC2 ERROR temp/tb_${1}_${2}.txt | head
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	exit 1
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fi
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exit 0
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			@ -21,7 +21,7 @@ python generate.py
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	for j in $( ls temp/brams_*.txt | sed 's,.*_,,; s,\..*,,;' | grep -v $i ); do
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		echo "temp/job_${i}_${j}.ok:"
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		echo "	@bash run-single.sh ${i} ${j}"
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		echo "	@echo 'Passed test ${i}_${j}.'"
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		echo "	@echo 'Passed memory_bram test ${i}_${j}.'"
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		echo "	@touch \$@"
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	done; done
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} > temp/makefile
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