3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00

clk2fflogic: Fix handling of $check cells

Fixes a bug in the handling of the recently introduced $check cells.
Both $check and $print cells in clk2fflogic are handled by the same code
and the existing tests for that were only using $print cells. This
missed a bug where the additional A signal of $check cells that is not
present on $print cells was dropped due to a typo, rendering $check
cells non-functional.

Also updates the tests to explicitly cover both cell types such that
they would have detected the now fixed bug.
This commit is contained in:
Jannis Harder 2024-02-14 11:42:27 +01:00
parent 91685355a0
commit bbdfcfdf30
3 changed files with 43 additions and 15 deletions

View file

@ -238,7 +238,8 @@ struct Clk2fflogicPass : public Pass {
cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
cell->setPort(ID::ARGS, sig_args_sampled);
if (cell->type == ID($check)) {
SigBit sig_a_sampled = sample_data(module, sig_en, State::S1, false, false).sampled;
SigBit sig_a = cell->getPort(ID::A);
SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
cell->setPort(ID::A, sig_a_sampled);
}
}