mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Added format __attribute__ to stringf()

Browse source
This commit is contained in:
Clifford Wolf 2014-10-10 17:22:08 +02:00
parent 7cb0d3aa1a
commit bbd808072b
5 changed files with 8 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
frontends/verilog/preproc.cc
View file

@ -422,7 +422,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
if (tok == "(" || tok == "{" || tok == "[") if (tok == "(" || tok == "{" || tok == "[")
level++; level++;
} }
for (size_t i = 0; i < args.size(); i++) for (int i = 0; i < GetSize(args); i++)
defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i]; defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i];
} else { } else {
insert_input(tok); insert_input(tok);

2
kernel/satgen.h
View file

@ -68,7 +68,7 @@ struct SatGen
else else
vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE); vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
} else { } else {
std::string name = pf + stringf(bit.wire->width == 1 ? "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset); std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset));
vec.push_back(ez->frozen_literal(name)); vec.push_back(ez->frozen_literal(name));
imported_signals[pf][bit] = vec.back(); imported_signals[pf][bit] = vec.back();
} }

2
kernel/yosys.h
View file

@ -82,7 +82,7 @@ namespace RTLIL {
struct Cell; struct Cell;
} }
std::string stringf(const char *fmt, ...); std::string stringf(const char *fmt, ...) __attribute__ ((format (printf, 1, 2)));
std::string vstringf(const char *fmt, va_list ap); std::string vstringf(const char *fmt, va_list ap);
template<typename T> int GetSize(const T &obj) { return obj.size(); } template<typename T> int GetSize(const T &obj) { return obj.size(); }
int GetSize(RTLIL::Wire *wire); int GetSize(RTLIL::Wire *wire);

2
passes/cmds/show.cc
View file

@ -72,7 +72,7 @@ struct ShowWorker
{ {
if (currentColor == 0) if (currentColor == 0)
return "color=\"black\""; return "color=\"black\"";
return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1); return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1, currentColor%8+1);
} }
std::string nextColor(std::string presetColor) std::string nextColor(std::string presetColor)

6
passes/techmap/techmap.cc
View file

@ -109,8 +109,10 @@ struct TechmapWorker
connbits_map.at(bit).second, log_id(connbits_map.at(bit).first)); connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
log_id(connbits_map.at(bit).first), connbits_map.at(bit).second); log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
} else } else {
connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data); connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
constmap_info += stringf("|%s %d", log_id(conn.first), i);
}
} }
return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str()); return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());