mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Remove SRL* delays from cells_sim.v

Browse source
This commit is contained in:
Eddie Hung 2019-08-20 18:14:40 -07:00
parent fad15d276d
commit bbab608691
1 changed files with 3 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/xilinx/cells_sim.v
View file

@ -342,8 +342,7 @@ module RAM128X1D (
endmodule
module SRL16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output Q,
output Q,
input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
@ -361,9 +360,8 @@ module SRL16E (
endmodule
module SRLC32E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output Q,
(* abc_arrival=1114 *) output Q31,
output Q,
output Q31,
input [4:0] A,
input CE, CLK, D
);