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abc9_ops: -reintegrate to handle $_FF_; cleanup

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This commit is contained in:
Eddie Hung 2020-04-16 14:03:54 -07:00
parent e357b40e7a
commit bb840cca9c
1 changed files with 18 additions and 22 deletions
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16
passes/techmap/abc9_ops.cc
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@ -166,6 +166,7 @@ void prep_dff_map(RTLIL::Design *design)
for (auto module : design->modules()) { for (auto module : design->modules()) {
vector<Cell*> specify_cells; vector<Cell*> specify_cells;
SigBit D, Q; SigBit D, Q;
Cell *c;
Cell* dff_cell = nullptr; Cell* dff_cell = nullptr;
// If module has a public name (i.e. not $paramod) and it doesn't exist // If module has a public name (i.e. not $paramod) and it doesn't exist
@ -217,9 +218,6 @@ void prep_dff_map(RTLIL::Design *design)
if (!dff_cell) if (!dff_cell)
log_error("Module '%s' with (* abc9_flop *) does not any contain $_DFF_[NP]_ cells.\n", log_id(module)); log_error("Module '%s' with (* abc9_flop *) does not any contain $_DFF_[NP]_ cells.\n", log_id(module));
D = dff_cell->getPort(ID::D);
{
// Add dummy buffers for all module inputs/outputs // Add dummy buffers for all module inputs/outputs
// to ensure that these ports exists in the flop box // to ensure that these ports exists in the flop box
// created by later submod pass // created by later submod pass
@ -233,12 +231,10 @@ void prep_dff_map(RTLIL::Design *design)
} }
// Add an additional buffer that drives $_DFF_[NP]_.D // Add an additional buffer that drives $_DFF_[NP]_.D
// so that the flop box will have an output // so that the flop box will have an output
auto w = module->addWire(NEW_ID); D = module->addWire(NEW_ID);
auto c = module->addBufGate(NEW_ID, D, w); c = module->addBufGate(NEW_ID, dff_cell->getPort(ID::D), D);
c->set_bool_attribute(ID::keep); c->set_bool_attribute(ID::keep);
dff_cell->setPort(ID::D, w); dff_cell->setPort(ID::D, D);
D = w;
}
// Rewrite $specify cells that end with $_DFF_[NP]_.Q // Rewrite $specify cells that end with $_DFF_[NP]_.Q
// to $_DFF_[NP]_.D since it will be moved into // to $_DFF_[NP]_.D since it will be moved into
@ -895,9 +891,9 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
std::map<IdString, int> cell_stats; std::map<IdString, int> cell_stats;
for (auto mapped_cell : mapped_mod->cells()) for (auto mapped_cell : mapped_mod->cells())
{ {
// Short out $_DFF_[NP]_ cells since the flop box already has // Short out $_FF_ cells since the flop box already has
// all the information we need to reconstruct cell // all the information we need to reconstruct cell
if (dff_mode && mapped_cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { if (dff_mode && mapped_cell->type == ID($_FF_)) {
SigBit D = mapped_cell->getPort(ID::D); SigBit D = mapped_cell->getPort(ID::D);
SigBit Q = mapped_cell->getPort(ID::Q); SigBit Q = mapped_cell->getPort(ID::Q);
if (D.wire) if (D.wire)