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Fix GHDL and bump yosys-slang

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This commit is contained in:
Akash Levy 2024-09-27 04:43:59 -07:00
parent 5a27db1463
commit bb2cdd61fe
2 changed files with 3 additions and 2 deletions
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3
frontends/verific/verific.cc
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@ -3768,7 +3768,8 @@ struct VerificPass : public Pass {
if (!FileSystem::PathExists(ghdl_path.c_str())) ghdl_path = "ghdl"; if (!FileSystem::PathExists(ghdl_path.c_str())) ghdl_path = "ghdl";
// Run command to convert VHDL to Verilog // Run command to convert VHDL to Verilog
std::string top = filename_str.substr(0, std::string(FileSystem::Basename(filename)).find_last_of(".")); std::string basename = FileSystem::Basename(filename);
std::string top = filename_str.substr(basename.find_last_of("/")+1, basename.find_last_of(".")-basename.find_last_of("/")-1);
std::string outfile = "preqorsor/data/" + top + ".v"; std::string outfile = "preqorsor/data/" + top + ".v";
std::string ghdl_cmd = ghdl_path + " --synth --no-formal -fsynopsys --out=verilog " + filename_str + " -e " + top + " > " + outfile; std::string ghdl_cmd = ghdl_path + " --synth --no-formal -fsynopsys --out=verilog " + filename_str + " -e " + top + " > " + outfile;
log("Running command: %s\n", ghdl_cmd.c_str()); log("Running command: %s\n", ghdl_cmd.c_str());

2
yosys-slang

@ -1 +1 @@
Subproject commit 59f2f6c74725315bb0bf75c0a520c514d738bf91 Subproject commit 8a548bb2fabe09dc949dafacae0495363e8f4d68