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https://github.com/YosysHQ/yosys
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Move GENERATE_PATTERN macro to separate utility header
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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parent
af61d92441
commit
bb0851bfc5
3 changed files with 157 additions and 128 deletions
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@ -23,13 +23,11 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// for peepopt_pm
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bool did_something;
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#include "passes/pmgen/test_pmgen_pm.h"
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#include "passes/pmgen/ice40_dsp_pm.h"
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#include "passes/pmgen/xilinx_srl_pm.h"
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#include "passes/pmgen/peepopt_pm.h"
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#include "generate.h"
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void reduce_chain(test_pmgen_pm &pm)
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{
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@ -118,123 +116,6 @@ void opt_eqpmux(test_pmgen_pm &pm)
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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#define GENERATE_PATTERN(pmclass, pattern) \
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generate_pattern<pmclass>([](pmclass &pm, std::function<void()> f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design)
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void pmtest_addports(Module *module)
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{
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pool<SigBit> driven_bits, used_bits;
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SigMap sigmap(module);
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int icnt = 0, ocnt = 0;
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for (auto cell : module->cells())
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for (auto conn : cell->connections())
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{
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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used_bits.insert(bit);
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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driven_bits.insert(bit);
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}
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for (auto wire : vector<Wire*>(module->wires()))
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{
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SigSpec ibits, obits;
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for (auto bit : sigmap(wire)) {
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if (!used_bits.count(bit))
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obits.append(bit);
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if (!driven_bits.count(bit))
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ibits.append(bit);
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}
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if (!ibits.empty()) {
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Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits));
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w->port_input = true;
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module->connect(ibits, w);
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}
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if (!obits.empty()) {
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Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits));
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w->port_output = true;
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module->connect(w, obits);
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}
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}
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module->fixup_ports();
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}
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template <class pm>
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void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const char *pmclass, const char *pattern, Design *design)
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{
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log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass);
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int modcnt = 0;
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int maxmodcnt = 100;
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int maxsubcnt = 4;
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int timeout = 0;
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vector<Module*> mods;
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while (modcnt < maxmodcnt)
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{
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int submodcnt = 0, itercnt = 0, cellcnt = 0;
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Module *mod = design->addModule(NEW_ID);
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while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000)
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{
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if (timeout++ > 10000)
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log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n");
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pm matcher(mod, mod->cells());
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matcher.rng(1);
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matcher.rngseed += modcnt;
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matcher.rng(1);
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matcher.rngseed += submodcnt;
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matcher.rng(1);
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matcher.rngseed += itercnt;
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matcher.rng(1);
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matcher.rngseed += cellcnt;
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matcher.rng(1);
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if (GetSize(mod->cells()) != cellcnt)
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{
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bool found_match = false;
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run(matcher, [&](){ found_match = true; });
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cellcnt = GetSize(mod->cells());
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if (found_match) {
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Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d",
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pmclass, pattern, modcnt++));
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log("Creating module %s with %d cells.\n", log_id(m), cellcnt);
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mod->cloneInto(m);
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pmtest_addports(m);
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mods.push_back(m);
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submodcnt++;
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timeout = 0;
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}
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}
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matcher.generate_mode = true;
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run(matcher, [](){});
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}
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if (submodcnt && maxsubcnt < (1 << 16))
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maxsubcnt *= 2;
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design->remove(mod);
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}
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Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern));
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log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods));
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for (auto mod : mods) {
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Cell *c = m->addCell(mod->name, mod->name);
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for (auto port : mod->ports) {
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Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port)));
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c->setPort(port, w);
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}
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}
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pmtest_addports(m);
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}
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struct TestPmgenPass : public Pass {
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TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { }
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void help() YS_OVERRIDE
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@ -355,12 +236,6 @@ struct TestPmgenPass : public Pass {
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if (pattern == "xilinx_srl.variable")
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return GENERATE_PATTERN(xilinx_srl_pm, variable);
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if (pattern == "peepopt-muldiv")
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return GENERATE_PATTERN(peepopt_pm, muldiv);
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if (pattern == "peepopt-shiftmul")
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return GENERATE_PATTERN(peepopt_pm, shiftmul);
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log_cmd_error("Unknown pattern: %s\n", pattern.c_str());
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}
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