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Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
This commit is contained in:
whitequark
GitHub
commit
baf1875307
33 changed files with 783 additions and 262 deletions
33
tests/simple/func_block.v
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33
tests/simple/func_block.v
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@ -0,0 +1,33 @@
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`default_nettype none
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module top(inp, out1, out2, out3);
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input wire [31:0] inp;
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function automatic [31:0] func1;
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input [31:0] inp;
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reg [31:0] idx;
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for (idx = 0; idx < 32; idx = idx + 1) begin : blk
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func1[idx] = (idx & 1'b1) ^ inp[idx];
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end
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endfunction
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function automatic [31:0] func2;
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input [31:0] inp;
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reg [31:0] idx;
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for (idx = 0; idx < 32; idx = idx + 1) begin : blk
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func2[idx] = (idx & 1'b1) ^ inp[idx];
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end
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endfunction
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function automatic [31:0] func3;
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localparam A = 32 - 1;
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parameter B = 1 - 0;
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input [31:0] inp;
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func3[A:B] = inp[A:B];
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endfunction
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output wire [31:0] out1, out2, out3;
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assign out1 = func1(inp);
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assign out2 = func2(inp);
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assign out3 = func3(inp);
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endmodule
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25
tests/simple/func_recurse.v
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25
tests/simple/func_recurse.v
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@ -0,0 +1,25 @@
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module top(
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input wire [3:0] inp,
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output wire [3:0] out1, out2
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);
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function automatic [3:0] pow_a;
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input [3:0] base, exp;
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begin
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pow_a = 1;
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if (exp > 0)
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pow_a = base * pow_a(base, exp - 1);
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end
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endfunction
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function automatic [3:0] pow_b;
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input [3:0] base, exp;
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begin
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pow_b = 1;
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if (exp > 0)
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pow_b = base * pow_b(base, exp - 1);
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end
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endfunction
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assign out1 = pow_a(inp, 3);
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assign out2 = pow_b(2, 2);
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endmodule
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41
tests/simple/func_width_scope.v
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41
tests/simple/func_width_scope.v
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@ -0,0 +1,41 @@
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module top(inp, out1, out2);
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input wire signed inp;
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localparam WIDTH_A = 5;
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function automatic [WIDTH_A-1:0] func1;
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input reg [WIDTH_A-1:0] inp;
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func1 = ~inp;
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endfunction
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wire [func1(0)-1:0] xc;
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assign xc = 1'sb1;
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wire [WIDTH_A-1:0] xn;
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assign xn = func1(inp);
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generate
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if (1) begin : blk
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localparam WIDTH_A = 6;
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function automatic [WIDTH_A-1:0] func2;
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input reg [WIDTH_A-1:0] inp;
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func2 = ~inp;
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endfunction
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wire [func2(0)-1:0] yc;
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assign yc = 1'sb1;
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wire [WIDTH_A-1:0] yn;
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assign yn = func2(inp);
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localparam WIDTH_B = 7;
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function automatic [WIDTH_B-1:0] func3;
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input reg [WIDTH_B-1:0] inp;
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func3 = ~inp;
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endfunction
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wire [func3(0)-1:0] zc;
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assign zc = 1'sb1;
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wire [WIDTH_B-1:0] zn;
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assign zn = func3(inp);
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end
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endgenerate
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output wire [1023:0] out1, out2;
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assign out1 = {xc, 1'b0, blk.yc, 1'b0, blk.zc};
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assign out2 = {xn, 1'b0, blk.yn, 1'b0, blk.zn};
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endmodule
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27
tests/simple/genblk_collide.v
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27
tests/simple/genblk_collide.v
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@ -0,0 +1,27 @@
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`default_nettype none
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module top1;
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generate
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if (1) begin : foo
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if (1) begin : bar
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wire x;
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end
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assign bar.x = 1;
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wire y;
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end
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endgenerate
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endmodule
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module top2;
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genvar i;
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generate
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if (1) begin : foo
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wire x;
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for (i = 0; i < 1; i = i + 1) begin : foo
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if (1) begin : foo
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assign x = 1;
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end
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end
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end
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endgenerate
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endmodule
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21
tests/simple/genblk_dive.v
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21
tests/simple/genblk_dive.v
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@ -0,0 +1,21 @@
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`default_nettype none
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module top(output wire x);
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generate
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if (1) begin : Z
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if (1) begin : A
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wire x;
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if (1) begin : B
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wire x;
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if (1) begin : C
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wire x;
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assign B.x = 0;
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wire z = A.B.C.x;
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end
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assign A.x = A.B.C.x;
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end
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assign B.C.x = B.x;
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end
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end
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endgenerate
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assign x = Z.A.x;
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endmodule
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18
tests/simple/genblk_order.v
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18
tests/simple/genblk_order.v
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@ -0,0 +1,18 @@
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`default_nettype none
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module top(
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output wire out1,
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output wire out2
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);
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generate
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if (1) begin : outer
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if (1) begin : foo
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wire x = 0;
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if (1) begin : foo
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wire x = 1;
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assign out1 = foo.x;
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end
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assign out2 = foo.x;
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end
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end
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endgenerate
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endmodule
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@ -260,3 +260,66 @@ module gen_test8;
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`ASSERT(gen_test8.A.C.x == 1)
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`ASSERT(gen_test8.A.B.x == 0)
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endmodule
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// ------------------------------------------
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module gen_test9;
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// `define VERIFY
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`ifdef VERIFY
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`define ASSERT(expr) assert property (expr);
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`else
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`define ASSERT(expr)
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`endif
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wire [1:0] w = 2'b11;
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generate
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begin : A
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wire [1:0] x;
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begin : B
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wire [1:0] y = 2'b00;
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`ASSERT(w == 3)
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`ASSERT(x == 2)
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`ASSERT(y == 0)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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end
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begin : C
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wire [1:0] z = 2'b01;
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`ASSERT(w == 3)
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`ASSERT(x == 2)
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`ASSERT(z == 1)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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end
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assign x = B.y ^ 2'b11 ^ C.z;
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`ASSERT(x == 2)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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end
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endgenerate
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`ASSERT(w == 3)
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`ASSERT(A.x == 2)
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`ASSERT(A.C.z == 1)
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`ASSERT(A.B.y == 0)
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`ASSERT(gen_test9.w == 3)
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`ASSERT(gen_test9.A.x == 2)
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`ASSERT(gen_test9.A.C.z == 1)
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`ASSERT(gen_test9.A.B.y == 0)
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endmodule
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11
tests/simple/local_loop_var.sv
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11
tests/simple/local_loop_var.sv
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module top(out);
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output integer out;
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initial begin
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integer i;
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for (i = 0; i < 5; i = i + 1)
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if (i == 0)
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out = 1;
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else
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out += 2 ** i;
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end
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endmodule
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15
tests/simple/loop_var_shadow.v
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15
tests/simple/loop_var_shadow.v
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module top(out);
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genvar i;
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generate
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for (i = 0; i < 2; i = i + 1) begin : loop
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localparam j = i + 1;
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if (1) begin : blk
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localparam i = j + 1;
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wire [i:0] x;
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assign x = 1'sb1;
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end
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end
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endgenerate
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output wire [63:0] out;
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assign out = {loop[0].blk.x, loop[1].blk.x};
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endmodule
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27
tests/simple/named_genblk.v
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27
tests/simple/named_genblk.v
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`default_nettype none
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module top;
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generate
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if (1) begin
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wire t;
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begin : foo
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wire x;
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end
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wire u;
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end
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begin : bar
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wire x;
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wire y;
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begin : baz
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wire x;
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wire z;
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end
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end
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endgenerate
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assign genblk1.t = 1;
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assign genblk1.foo.x = 1;
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assign genblk1.u = 1;
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assign bar.x = 1;
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assign bar.y = 1;
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assign bar.baz.x = 1;
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assign bar.baz.z = 1;
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endmodule
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14
tests/simple/nested_genblk_resolve.v
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14
tests/simple/nested_genblk_resolve.v
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@ -0,0 +1,14 @@
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`default_nettype none
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module top;
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generate
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if (1) begin
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wire x;
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genvar i;
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for (i = 0; i < 1; i = i + 1) begin
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if (1) begin
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assign x = 1;
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end
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end
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end
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endgenerate
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endmodule
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17
tests/simple/unnamed_block_decl.sv
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17
tests/simple/unnamed_block_decl.sv
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@ -0,0 +1,17 @@
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module top(z);
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output integer z;
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initial begin
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integer x;
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x = 1;
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begin
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integer y;
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y = x + 1;
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begin
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integer z;
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z = y + 1;
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y = z + 1;
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end
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z = y + 1;
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end
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end
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endmodule
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