From bade16eb23c6b4d64790e52ed9312a3ce580ff4b Mon Sep 17 00:00:00 2001 From: Iztok Jeras Date: Fri, 31 Jul 2026 02:20:56 +0200 Subject: [PATCH] dfflibmap: changed error warning from 'wide' to 'word-level' to match documentation --- passes/techmap/dfflibmap.cc | 4 ++-- .../techmap/{dfflibmap_wide.ys => dfflibmap_world_level.ys} | 0 tests/techmap/dlatchlibmap_world_level.ys | 5 +++++ 3 files changed, 7 insertions(+), 2 deletions(-) rename tests/techmap/{dfflibmap_wide.ys => dfflibmap_world_level.ys} (100%) create mode 100644 tests/techmap/dlatchlibmap_world_level.ys diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 1a66f12d5..b1d510b8e 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -602,8 +602,8 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) for (auto cell : module->cells()) { auto cats = StaticCellTypes::categories; if (cats.is_ff(cell->type) && !cats.is_stdcell(cell->type)) - log_error("Wide register cell type %s is not supported.\n" - "Convert netlist to gate-level first.\n", cell->type); + log_error("Word-level register cell type %s is not supported.\n" + "Convert netlist to gate-level first (by running 'techmap').\n", cell->type); if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0) cell_list.push_back(cell); diff --git a/tests/techmap/dfflibmap_wide.ys b/tests/techmap/dfflibmap_world_level.ys similarity index 100% rename from tests/techmap/dfflibmap_wide.ys rename to tests/techmap/dfflibmap_world_level.ys diff --git a/tests/techmap/dlatchlibmap_world_level.ys b/tests/techmap/dlatchlibmap_world_level.ys new file mode 100644 index 000000000..ed8dd31e4 --- /dev/null +++ b/tests/techmap/dlatchlibmap_world_level.ys @@ -0,0 +1,5 @@ +read_verilog ../sim/dlatch.v +proc +logger -expect error "not supported" 1 +dfflibmap -liberty dlatchlibmap.lib +logger -check-expected