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Update passes/opt to avoid bits()

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This commit is contained in:
Robert O'Callahan 2025-08-28 03:53:23 +00:00
parent d4e2fa0c4f
commit bab72e0af7
10 changed files with 71 additions and 56 deletions
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6
passes/opt/opt_clean.cc
View file

@ -406,7 +406,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
for (int i = 0; i < wire->width; i++) {
auto it = init_bits.find(RTLIL::SigBit(wire, i));
if (it != init_bits.end()) {
val.bits()[i] = it->second;
val.set(i, it->second);
found = true;
}
}
@ -425,7 +425,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire))
initval.bits().resize(GetSize(wire), State::Sx);
initval.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef())
wire->attributes.erase(ID::init);
@ -457,7 +457,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (s1[i] != s2[i]) {
if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) {
s2[i] = initval[i];
initval.bits()[i] = State::Sx;
initval.set(i, State::Sx);
}
new_conn.first.append(s1[i]);
new_conn.second.append(s2[i]);

22
passes/opt/opt_dff.cc
View file

@ -405,27 +405,29 @@ struct OptDffWorker
} else if (ff.pol_clr == ff.pol_set) {
// Try a more complex conversion to plain async reset.
State val_neutral = ff.pol_set ? State::S0 : State::S1;
Const val_arst;
SigBit sig_arst;
if (ff.sig_clr[0] == val_neutral)
sig_arst = ff.sig_set[0];
else
sig_arst = ff.sig_clr[0];
bool failed = false;
Const::Builder val_arst_builder(ff.width);
for (int i = 0; i < ff.width; i++) {
if (ff.sig_clr[i] == sig_arst && ff.sig_set[i] == val_neutral)
val_arst.bits().push_back(State::S0);
val_arst_builder.push_back(State::S0);
else if (ff.sig_set[i] == sig_arst && ff.sig_clr[i] == val_neutral)
val_arst.bits().push_back(State::S1);
else
val_arst_builder.push_back(State::S1);
else {
failed = true;
break;
}
}
if (!failed) {
log("Converting CLR/SET to ARST on %s (%s) from module %s.\n",
log_id(cell), log_id(cell->type), log_id(module));
ff.has_sr = false;
ff.has_arst = true;
ff.val_arst = val_arst;
ff.val_arst = val_arst_builder.build();
ff.sig_arst = sig_arst;
ff.pol_arst = ff.pol_clr;
changed = true;
@ -637,7 +639,7 @@ struct OptDffWorker
// Try to merge sync resets.
std::map<ctrls_t, std::vector<int>> groups;
std::vector<int> remaining_indices;
Const val_srst;
Const::Builder val_srst_builder(ff.width);
for (int i = 0 ; i < ff.width; i++) {
ctrls_t resets;
@ -679,16 +681,18 @@ struct OptDffWorker
groups[resets].push_back(i);
} else
remaining_indices.push_back(i);
val_srst.bits().push_back(reset_val);
val_srst_builder.push_back(reset_val);
}
Const val_srst = val_srst_builder.build();
for (auto &it : groups) {
FfData new_ff = ff.slice(it.second);
new_ff.val_srst = Const();
Const::Builder new_val_srst_builder(new_ff.width);
for (int i = 0; i < new_ff.width; i++) {
int j = it.second[i];
new_ff.val_srst.bits().push_back(val_srst[j]);
new_val_srst_builder.push_back(val_srst[j]);
}
new_ff.val_srst = new_val_srst_builder.build();
ctrl_t srst = combine_resets(it.first, ff.is_fine);
new_ff.has_srst = true;

4
passes/opt/opt_expr.cc
View file

@ -83,7 +83,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
auto cursor = initbits.find(bit);
if (cursor != initbits.end()) {
revisit_initwires.insert(cursor->second.first);
val.bits()[i] = cursor->second.second;
val.set(i, cursor->second.second);
}
}
@ -101,7 +101,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval.bits()[i] = State::Sx;
initval.set(i, State::Sx);
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));

15
passes/opt/opt_ffinv.cc
View file

@ -96,10 +96,10 @@ struct OptFfInvWorker
}
}
Const mask = lut->getParam(ID::LUT);
Const new_mask;
for (int j = 0; j < (1 << GetSize(sig_a)); j++) {
new_mask.bits().push_back(mask[j ^ flip_mask]);
}
Const::Builder new_mask_builder(1 << GetSize(sig_a));
for (int j = 0; j < (1 << GetSize(sig_a)); j++)
new_mask_builder.push_back(mask[j ^ flip_mask]);
Const new_mask = new_mask_builder.build();
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->remove(lut);
@ -178,13 +178,14 @@ struct OptFfInvWorker
if (d_lut->type == ID($lut)) {
Const mask = d_lut->getParam(ID::LUT);
Const new_mask;
Const::Builder new_mask_builder(GetSize(mask));
for (int i = 0; i < GetSize(mask); i++) {
if (mask[i] == State::S0)
new_mask.bits().push_back(State::S1);
new_mask_builder.push_back(State::S1);
else
new_mask.bits().push_back(State::S0);
new_mask_builder.push_back(State::S0);
}
Const new_mask = new_mask_builder.build();
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {
module->connect(ff.sig_d, d_lut->getPort(ID::A));

2
passes/opt/opt_lut.cc
View file

@ -493,7 +493,7 @@ struct OptLutWorker
eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
}
eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs);
lutM_new_table.bits()[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
lutM_new_table.set(eval, (RTLIL::State) evaluate_lut(lutB, eval_inputs));
}
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());

2
passes/opt/opt_lut_ins.cc
View file

@ -213,7 +213,7 @@ struct OptLutInsPass : public Pass {
}
lidx |= val << j;
}
new_lut.bits()[i] = lut[lidx];
new_lut.set(i, lut[lidx]);
}
// For lattice, and gowin do not replace with a const driver — the nextpnr
// packer requires a complete set of LUTs for wide LUT muxes.

30
passes/opt/opt_mem.cc
View file

@ -175,36 +175,36 @@ struct OptMemPass : public Pass {
}
for (auto &port: mem.rd_ports) {
SigSpec new_data;
Const new_init;
Const new_arst;
Const new_srst;
Const::Builder new_init_bits;
Const::Builder new_arst_bits;
Const::Builder new_srst_bits;
for (int sub = 0; sub < (1 << port.wide_log2); sub++) {
for (auto i: swizzle) {
int bidx = sub * mem.width + i;
new_data.append(port.data[bidx]);
new_init.bits().push_back(port.init_value[bidx]);
new_arst.bits().push_back(port.arst_value[bidx]);
new_srst.bits().push_back(port.srst_value[bidx]);
new_init_bits.push_back(port.init_value[bidx]);
new_arst_bits.push_back(port.arst_value[bidx]);
new_srst_bits.push_back(port.srst_value[bidx]);
}
}
port.data = new_data;
port.init_value = new_init;
port.arst_value = new_arst;
port.srst_value = new_srst;
port.init_value = new_init_bits.build();
port.arst_value = new_arst_bits.build();
port.srst_value = new_srst_bits.build();
}
for (auto &init: mem.inits) {
Const new_data;
Const new_en;
Const::Builder new_data_bits;
for (int s = 0; s < GetSize(init.data); s += mem.width) {
for (auto i: swizzle) {
new_data.bits().push_back(init.data[s + i]);
new_data_bits.push_back(init.data[s + i]);
}
}
init.data = new_data_bits.build();
Const::Builder new_en_bits;
for (auto i: swizzle) {
new_en.bits().push_back(init.en[i]);
new_en_bits.push_back(init.en[i]);
}
init.data = new_data;
init.en = new_en;
init.en = new_en_bits.build();
}
mem.width = GetSize(swizzle);
changed = true;

16
passes/opt/pmux2shiftx.cc
View file

@ -321,11 +321,12 @@ struct Pmux2ShiftxPass : public Pass {
bits.sort();
pair<SigSpec, Const> entry;
RTLIL::Const::Builder entry_bits_builder(GetSize(bits));
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits().push_back(it.second);
entry_bits_builder.push_back(it.second);
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
goto next_cell;
@ -342,11 +343,12 @@ struct Pmux2ShiftxPass : public Pass {
bits.sort();
pair<SigSpec, Const> entry;
RTLIL::Const::Builder entry_bits_builder(GetSize(bits));
for (auto it : bits) {
entry.first.append(it.first);
entry.second.bits().push_back(it.second);
entry_bits_builder.push_back(it.second);
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
goto next_cell;
@ -591,7 +593,7 @@ struct Pmux2ShiftxPass : public Pass {
used_src_columns[best_src_col] = true;
perm_new_from_old[dst_col] = best_src_col;
perm_xormask.bits()[dst_col] = best_inv ? State::S1 : State::S0;
perm_xormask.set(dst_col, best_inv ? State::S1 : State::S0);
}
}
@ -614,7 +616,7 @@ struct Pmux2ShiftxPass : public Pass {
Const new_c(State::S0, GetSize(old_c));
for (int i = 0; i < GetSize(old_c); i++)
new_c.bits()[i] = old_c[perm_new_from_old[i]];
new_c.set(i, old_c[perm_new_from_old[i]]);
Const new_c_before_xor = new_c;
new_c = const_xor(new_c, perm_xormask, false, false, GetSize(new_c));
@ -687,7 +689,7 @@ struct Pmux2ShiftxPass : public Pass {
if (!full_case) {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.bits()[it.first.as_int()] = State::S1;
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
}

26
passes/opt/share.cc
View file

@ -790,12 +790,13 @@ struct ShareWorker
}
p.first = RTLIL::SigSpec();
p.second.bits().clear();
RTLIL::Const::Builder new_bits(p_bits.size());
for (auto &it : p_bits) {
p.first.append(it.first);
p.second.bits().push_back(it.second);
new_bits.push_back(it.second);
}
p.second = new_bits.build();
return true;
}
@ -818,9 +819,9 @@ struct ShareWorker
auto otherval = val;
if (otherval[i] == State::S0)
otherval.bits()[i] = State::S1;
otherval.set(i, State::S1);
else if (otherval[i] == State::S1)
otherval.bits()[i] = State::S0;
otherval.set(i, State::S0);
else
continue;
@ -829,8 +830,11 @@ struct ShareWorker
auto newsig = sig;
newsig.remove(i);
auto newval = val;
newval.bits().erase(newval.bits().begin() + i);
RTLIL::Const::Builder new_bits(val.size() - 1);
for (int j = 0; j < val.size(); ++j)
if (j != i)
new_bits.push_back(val[j]);
RTLIL::Const newval = new_bits.build();
db[newsig].insert(newval);
db[sig].erase(otherval);
@ -926,7 +930,8 @@ struct ShareWorker
if (used_in_a)
for (auto p : c_patterns) {
for (int i = 0; i < GetSize(sig_s); i++)
p.first.append(sig_s[i]), p.second.bits().push_back(RTLIL::State::S0);
p.first.append(sig_s[i]);
p.second.append(RTLIL::Const(RTLIL::State::S0, GetSize(sig_s)));
if (sort_check_activation_pattern(p))
if (!insert_capped(activation_patterns_cache[cell], p)) {
recursion_state.erase(cell);
@ -936,7 +941,8 @@ struct ShareWorker
for (int idx : used_in_b_parts)
for (auto p : c_patterns) {
p.first.append(sig_s[idx]), p.second.bits().push_back(RTLIL::State::S1);
p.first.append(sig_s[idx]);
p.second.append(RTLIL::Const(RTLIL::State::S1));
if (sort_check_activation_pattern(p))
if (!insert_capped(activation_patterns_cache[cell], p)) {
recursion_state.erase(cell);
@ -989,12 +995,14 @@ struct ShareWorker
{
std::vector<RTLIL::SigBit> p_first = p.first;
ssc_pair_t new_p;
RTLIL::Const::Builder new_p_second_bits;
for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
new_p.first.append(p_first[i]);
new_p.second.bits().push_back(p.second.at(i));
new_p_second_bits.push_back(p.second.at(i));
}
new_p.second = new_p_second_bits.build();
out.insert(new_p);
}

4
passes/opt/wreduce.cc
View file

@ -220,10 +220,10 @@ struct WreduceWorker
// Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID::ARST_VALUE)) {
rst_value.bits().resize(GetSize(sig_q));
rst_value.resize(GetSize(sig_q), State::S0);
cell->setParam(ID::ARST_VALUE, rst_value);
} else if (cell->parameters.count(ID::SRST_VALUE)) {
rst_value.bits().resize(GetSize(sig_q));
rst_value.resize(GetSize(sig_q), State::S0);
cell->setParam(ID::SRST_VALUE, rst_value);
}