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Update passes/opt to avoid bits()

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This commit is contained in:
Robert O'Callahan 2025-08-28 03:53:23 +00:00
parent d4e2fa0c4f
commit bab72e0af7
10 changed files with 71 additions and 56 deletions
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4
passes/opt/opt_expr.cc
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@ -83,7 +83,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
auto cursor = initbits.find(bit);
if (cursor != initbits.end()) {
revisit_initwires.insert(cursor->second.first);
val.bits()[i] = cursor->second.second;
val.set(i, cursor->second.second);
}
}
@ -101,7 +101,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i])
initval.bits()[i] = State::Sx;
initval.set(i, State::Sx);
}
if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));