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tests: Add bug3515

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This commit is contained in:
Krystine Sherwin 2025-11-25 07:04:34 +13:00
parent 38a1e66145
commit ba31a02578
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21
tests/various/bug3515.ys Normal file
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@ -0,0 +1,21 @@
read_verilog << EOF
module mod_and_or (
input a,
input b,
input c,
input d,
output reg y
);
always @(a,b,c,d) begin
y <= (a&b)|(c&d);
end
endmodule
EOF
hierarchy -top mod_and_or
proc
opt
techmap -map ./bug3515.v
proc
extract -map ./bug3515.v -verbose
proc