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https://github.com/YosysHQ/yosys
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Move from cell attr to module attr
This commit is contained in:
Eddie Hung
parent
2f4e0a5388
commit
ba2261e21a
2 changed files with 76 additions and 42 deletions
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@ -1202,7 +1202,15 @@ struct Abc9Pass : public Pass {
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std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
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pool<IdString> seen_cells;
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dict<IdString, std::pair<RTLIL::IdString,RTLIL::IdString>> flop_data;
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struct flop_data_t {
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IdString clk_port;
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IdString clk_pol_param;
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bool clk_pol;
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IdString en_port;
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IdString en_pol_param;
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bool en_pol;
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};
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dict<IdString, flop_data_t> flop_data;
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for (auto cell : all_cells) {
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clkdomain_t key;
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@ -1253,7 +1261,40 @@ struct Abc9Pass : public Pass {
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log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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if (abc_flop_en == IdString())
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log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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it = flop_data.insert(std::make_pair(cell->type, std::make_pair(abc_flop_clk, abc_flop_en))).first;
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auto jt = inst_module->attributes.find("\\abc_flop_clk_pol");
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if (jt == inst_module->attributes.end())
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log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(inst_module));
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IdString abc_flop_clk_pol_param;
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bool abc_flop_clk_pol;
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if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
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auto param = jt->second.decode_string();
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abc_flop_clk_pol = (param[0] == '!');
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if (abc_flop_clk_pol)
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abc_flop_clk_pol_param = RTLIL::escape_id(param.substr(1));
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else
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abc_flop_clk_pol_param = RTLIL::escape_id(param);
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}
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else
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abc_flop_clk_pol = !jt->second.as_bool();
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jt = inst_module->attributes.find("\\abc_flop_en_pol");
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if (jt == inst_module->attributes.end())
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log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(inst_module));
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IdString abc_flop_en_pol_param;
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bool abc_flop_en_pol;
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if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
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auto param = jt->second.decode_string();
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abc_flop_en_pol = (param[0] == '!');
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if (abc_flop_en_pol)
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abc_flop_en_pol_param = RTLIL::escape_id(param.substr(1));
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else
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abc_flop_en_pol_param = RTLIL::escape_id(param);
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}
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else
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abc_flop_en_pol = !jt->second.as_bool();
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it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_clk_pol_param, abc_flop_clk_pol,
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abc_flop_en, abc_flop_en_pol_param, abc_flop_en_pol})).first;
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}
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else {
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it = flop_data.find(cell->type);
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@ -1261,35 +1302,34 @@ struct Abc9Pass : public Pass {
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continue;
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}
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auto jt = cell->attributes.find("\\abc_flop_clk_pol");
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if (jt == cell->parameters.end())
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log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(cell->type));
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bool this_clk_pol;
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if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
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auto param = jt->second.decode_string();
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auto kt = cell->parameters.find(param);
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if (kt == cell->parameters.end())
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log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
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this_clk_pol = kt->second.as_bool();
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}
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else
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this_clk_pol = jt->second.as_bool();
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jt = cell->parameters.find("\\$abc_flop_en_pol");
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if (jt == cell->parameters.end())
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log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(cell->type));
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bool this_en_pol;
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if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
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auto param = jt->second.decode_string();
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auto kt = cell->parameters.find(param);
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if (kt == cell->parameters.end())
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log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
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this_en_pol = kt->second.as_bool();
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}
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else
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this_en_pol = jt->second.as_bool();
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const auto &data = it->second;
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key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second)));
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bool this_clk_pol;
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if (data.clk_pol_param == IdString())
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this_clk_pol = data.clk_pol;
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else {
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auto param = data.clk_pol_param;
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auto jt = cell->parameters.find(param);
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if (jt == cell->parameters.end())
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log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
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this_clk_pol = jt->second.as_bool();
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if (data.clk_pol)
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this_clk_pol = !this_clk_pol;
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}
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bool this_en_pol;
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if (data.en_pol_param == IdString())
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this_en_pol = data.en_pol;
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else {
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auto param = data.en_pol_param;
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auto jt = cell->parameters.find(param);
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if (jt == cell->parameters.end())
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log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
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this_en_pol = jt->second.as_bool();
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if (data.en_pol)
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this_en_pol = !this_en_pol;
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}
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key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.clk_port)), this_en_pol, assign_map(cell->getPort(data.en_port)));
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unassigned_cells.erase(cell);
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expand_queue.insert(cell);
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@ -26,7 +26,6 @@ module FDRE (output reg Q, input C, CE, D, R);
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_R_INVERTED = 1'b0;
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wire \$nextQ ;
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(* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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\$__ABC_FDRE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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@ -40,7 +39,6 @@ endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ ;
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(* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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\$__ABC_FDRE_1 #(.INIT(|0)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
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@ -54,7 +52,6 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_CLR_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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(* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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\$__ABC_FDCE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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@ -69,7 +66,6 @@ endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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(* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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\$__ABC_FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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@ -85,7 +81,6 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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parameter [0:0] IS_D_INVERTED = 1'b0;
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parameter [0:0] IS_PRE_INVERTED = 1'b0;
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wire \$nextQ , \$currQ ;
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(* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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\$__ABC_FDPE #(
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.INIT(INIT),
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.IS_C_INVERTED(IS_C_INVERTED),
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@ -100,7 +95,6 @@ endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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parameter [0:0] INIT = 1'b0;
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wire \$nextQ , \$currQ ;
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(* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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\$__ABC_FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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@ -118,7 +112,7 @@ endmodule
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module \$__ABC_ASYNC (input A, S, output Y);
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endmodule
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(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
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(* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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module \$__ABC_FDRE ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -131,7 +125,7 @@ module \$__ABC_FDRE ((* abc_flop_q *) output Q,
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assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
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endmodule
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(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
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(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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module \$__ABC_FDRE_1 ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -141,7 +135,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *) output Q,
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assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
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endmodule
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(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
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(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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module \$__ABC_FDCE ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -154,7 +148,7 @@ module \$__ABC_FDCE ((* abc_flop_q *) output Q,
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assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
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(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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module \$__ABC_FDCE_1 ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -164,7 +158,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *) output Q,
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assign Q = (CE && !CLR) ? D : \$pastQ ;
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endmodule
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(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
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(* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
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module \$__ABC_FDPE ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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@ -177,7 +171,7 @@ module \$__ABC_FDPE ((* abc_flop_q *) output Q,
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assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
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endmodule
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(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
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(* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
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module \$__ABC_FDPE_1 ((* abc_flop_q *) output Q,
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(* abc_flop_clk *) input C,
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(* abc_flop_en *) input CE,
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