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https://github.com/YosysHQ/yosys
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Refactor hierarchy wand/wor handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
e3ebac44df
commit
ba2185ead8
3 changed files with 163 additions and 121 deletions
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@ -562,7 +562,8 @@ struct HierarchyPass : public Pass {
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log("In parametric designs, a module might exists in several variations with\n");
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log("different parameter values. This pass looks at all modules in the current\n");
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log("design an re-runs the language frontends for the parametric modules as\n");
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log("needed. It also resolves assignments to wired logic data types (wand/wor).\n");
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log("needed. It also resolves assignments to wired logic data types (wand/wor),\n");
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log("resolves positional module parameters, unroll array instances, and more.\n");
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log("\n");
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log(" -check\n");
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log(" also check the design hierarchy. this generates an error when\n");
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@ -941,140 +942,180 @@ struct HierarchyPass : public Pass {
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std::set<Module*> blackbox_derivatives;
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std::vector<Module*> design_modules = design->modules();
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std::map<Wire*, Cell*> wlogic_map;
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for (auto module : design_modules)
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for (auto wire : module->wires())
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{
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Cell *reduce = nullptr;
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if (wire->get_bool_attribute("\\wand")) {
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reduce = module->addCell(
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stringf("$%s_reduce", wire->name.c_str()), "$reduce_and");
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}
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if (wire->get_bool_attribute("\\wor")) {
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reduce = module->addCell(
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stringf("$%s_reduce", wire->name.c_str()), "$reduce_or");
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}
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if (reduce) {
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if (wire->width > 1)
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log_error("Multi-bit wand/wor unsupported (%s)\n",
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log_id(wire));
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pool<Wire*> wand_wor_index;
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dict<Wire*, SigSpec> wand_map, wor_map;
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vector<SigSig> new_connections;
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reduce->parameters["\\A_SIGNED"] = Const(0);
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reduce->parameters["\\A_WIDTH"] = Const(0);
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reduce->setPort("\\A", SigSpec());
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reduce->parameters["\\Y_WIDTH"] = Const(1);
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reduce->setPort("\\Y", wire);
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wlogic_map[wire] = reduce;
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for (auto wire : module->wires())
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{
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if (wire->get_bool_attribute("\\wand")) {
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wand_map[wire] = SigSpec();
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wand_wor_index.insert(wire);
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}
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if (wire->get_bool_attribute("\\wor")) {
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wor_map[wire] = SigSpec();
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wand_wor_index.insert(wire);
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}
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}
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}
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for (auto module : design_modules) {
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std::vector<SigSig> new_connections;
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for (auto &conn : module->connections())
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{
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SigSpec sig = conn.first;
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for (int i = 0; i < GetSize(sig); i++) {
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Wire *sigwire = sig[i].wire;
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if (sigwire == nullptr)
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continue;
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SigSig new_conn;
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int cursor = 0;
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if (sigwire->get_bool_attribute("\\wor") || sigwire->get_bool_attribute("\\wand")) {
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Cell *reduce = wlogic_map[sigwire];
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SigSpec reduce_in = reduce->getPort("\\A");
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int reduce_width = reduce->getParam("\\A_WIDTH").as_int();
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Wire *new_reduce_input = module->addWire(
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stringf("%s_in%d", reduce->name.c_str(), reduce_width));
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reduce_in.append(new_reduce_input);
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reduce->setPort("\\A", reduce_in);
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reduce->fixup_parameters();
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sig[i] = new_reduce_input;
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}
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}
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new_connections.push_back(SigSig(sig, conn.second));
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}
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module->new_connections(new_connections);
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}
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for (auto module : design_modules)
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for (auto cell : module->cells())
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{
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Module *m = design->module(cell->type);
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if (m == nullptr)
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continue;
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if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (new_m_name.empty())
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continue;
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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}
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}
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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if (w == nullptr || w->port_id == 0)
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continue;
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if (GetSize(conn.second) == 0)
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continue;
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SigSpec sig = conn.second;
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if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
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for (auto c : conn.first.chunks())
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{
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if (GetSize(w) < GetSize(conn.second))
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{
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int n = GetSize(conn.second) - GetSize(w);
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if (!w->port_input && w->port_output)
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module->connect(sig.extract(GetSize(w), n), Const(0, n));
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sig.remove(GetSize(w), n);
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}
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else
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{
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int n = GetSize(w) - GetSize(conn.second);
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if (w->port_input && !w->port_output)
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sig.append(Const(0, n));
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else
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sig.append(module->addWire(NEW_ID, n));
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}
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Wire *w = c.wire;
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SigSpec rhs = conn.second.extract(cursor, GetSize(c));
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if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
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log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
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log_id(conn.first), GetSize(conn.second), GetSize(sig));
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cell->setPort(conn.first, sig);
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}
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for (int i = 0; i < GetSize(sig); i++) {
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Wire *sigwire = sig[i].wire;
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if (sigwire == nullptr)
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continue;
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if (sigwire->get_bool_attribute("\\wor") || sigwire->get_bool_attribute("\\wand")) {
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if (w->port_output && !w->port_input) {
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Cell *reduce = wlogic_map[sigwire];
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SigSpec reduce_in = reduce->getPort("\\A");
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int reduce_width = reduce->getParam("\\A_WIDTH").as_int();
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Wire *new_reduce_input = module->addWire(
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stringf("$%s_in%d", reduce->name.c_str(), reduce_width));
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reduce_in.append(new_reduce_input);
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reduce->setPort("\\A", reduce_in);
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reduce->fixup_parameters();
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sig[i] = new_reduce_input;
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if (wand_wor_index.count(w) == 0) {
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new_conn.first.append(c);
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new_conn.second.append(rhs);
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} else {
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if (wand_map.count(w)) {
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SigSpec sig = SigSpec(State::S1, GetSize(w));
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sig.replace(c.offset, rhs);
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wand_map.at(w).append(sig);
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} else {
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SigSpec sig = SigSpec(State::S0, GetSize(w));
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sig.replace(c.offset, rhs);
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wor_map.at(w).append(sig);
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}
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}
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cursor += GetSize(c);
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}
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cell->setPort(conn.first, sig);
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new_connections.push_back(new_conn);
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}
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module->new_connections(new_connections);
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if (w->port_output && !w->port_input && sig.has_const())
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log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
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log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
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for (auto cell : module->cells())
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{
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if (!cell->known())
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continue;
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for (auto &conn : cell->connections())
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{
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if (!cell->output(conn.first))
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continue;
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SigSpec new_sig;
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bool update_port = false;
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for (auto c : conn.second.chunks())
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{
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Wire *w = c.wire;
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if (wand_wor_index.count(w) == 0) {
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new_sig.append(c);
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continue;
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}
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Wire *t = module->addWire(NEW_ID, GetSize(c));
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new_sig.append(t);
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update_port = true;
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if (wand_map.count(w)) {
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SigSpec sig = SigSpec(State::S1, GetSize(w));
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sig.replace(c.offset, t);
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wand_map.at(w).append(sig);
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} else {
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SigSpec sig = SigSpec(State::S0, GetSize(w));
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sig.replace(c.offset, t);
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wor_map.at(w).append(sig);
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}
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}
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if (update_port)
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cell->setPort(conn.first, new_sig);
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}
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}
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for (auto w : wand_wor_index)
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{
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bool wand = wand_map.count(w);
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SigSpec sigs = wand ? wand_map.at(w) : wor_map.at(w);
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if (GetSize(sigs) == 0)
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continue;
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if (GetSize(w) == 1) {
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if (wand)
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module->addReduceAnd(NEW_ID, sigs, w);
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else
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module->addReduceOr(NEW_ID, sigs, w);
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continue;
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}
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SigSpec s = sigs.extract(0, GetSize(w));
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for (int i = GetSize(w); i < GetSize(sigs); i += GetSize(w)) {
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if (wand)
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s = module->And(NEW_ID, s, sigs.extract(i, GetSize(w)));
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else
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s = module->Or(NEW_ID, s, sigs.extract(i, GetSize(w)));
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}
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module->connect(w, s);
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}
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for (auto cell : module->cells())
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{
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Module *m = design->module(cell->type);
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if (m == nullptr)
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continue;
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if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
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IdString new_m_name = m->derive(design, cell->parameters, true);
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if (new_m_name.empty())
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continue;
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if (new_m_name != m->name) {
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m = design->module(new_m_name);
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blackbox_derivatives.insert(m);
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}
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}
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for (auto &conn : cell->connections())
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{
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Wire *w = m->wire(conn.first);
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if (w == nullptr || w->port_id == 0)
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continue;
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if (GetSize(conn.second) == 0)
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continue;
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SigSpec sig = conn.second;
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if (!keep_portwidths && GetSize(w) != GetSize(conn.second))
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{
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if (GetSize(w) < GetSize(conn.second))
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{
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int n = GetSize(conn.second) - GetSize(w);
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if (!w->port_input && w->port_output)
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module->connect(sig.extract(GetSize(w), n), Const(0, n));
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sig.remove(GetSize(w), n);
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}
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else
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{
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int n = GetSize(w) - GetSize(conn.second);
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if (w->port_input && !w->port_output)
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sig.append(Const(0, n));
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else
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sig.append(module->addWire(NEW_ID, n));
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}
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if (!conn.second.is_fully_const() || !w->port_input || w->port_output)
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log_warning("Resizing cell port %s.%s.%s from %d bits to %d bits.\n", log_id(module), log_id(cell),
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log_id(conn.first), GetSize(conn.second), GetSize(sig));
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cell->setPort(conn.first, sig);
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}
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if (w->port_output && !w->port_input && sig.has_const())
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log_error("Output port %s.%s.%s (%s) is connected to constants: %s\n",
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log_id(module), log_id(cell), log_id(conn.first), log_id(cell->type), log_signal(sig));
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}
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}
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}
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