mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-04 00:58:10 +00:00
Code Activity

Various documentation updates

Browse source
This commit is contained in:
Clifford Wolf 2014-11-08 10:59:48 +01:00
parent 420bc05627
commit b9f2127f5d
13 changed files with 1277 additions and 108 deletions
Download patch file Download diff file Expand all files Collapse all files

6
manual/PRESENTATION_ExSyn.tex
View file

@ -268,7 +268,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
@ -455,7 +455,7 @@ read_verilog -D WITH_MULT cpu_alu.v
hierarchy -check -top cpu_top
# high-level synthesis
proc; opt; memory -nomap;; fsm; opt
proc; opt; fsm;; memory -nomap; opt
# substitute block rams
techmap -map map_rams.v
@ -497,7 +497,7 @@ the next part (Section 3, ``Advanced Synthesis'') of this presentation.}
\item Yosys provides commands for each phase of the synthesis.
\item Each command solves a (more or less) simple problem.
\item Complex commands are often only front-ends to simple commands.
\item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
\item {\tt proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;}
\end{itemize}
\bigskip