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Various documentation updates

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Clifford Wolf 2014-11-08 10:59:48 +01:00
parent 420bc05627
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manual/CHAPTER_Appnotes.tex
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@ -2,11 +2,24 @@
\chapter{Application Notes}
\label{chapter:appnotes}
\begin{fixme}
This appendix will cover some typical use-cases of Yosys in the form of application notes.
\end{fixme}
% \begin{fixme}
% This appendix will cover some typical use-cases of Yosys in the form of application notes.
% \end{fixme}
%
% \section{Synthesizing using a Cell Library in Liberty Format}
% \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
% \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
\section{Synthesizing using a Cell Library in Liberty Format}
\section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
\section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
This appendix contains copies of the Yosys application notes.
\begin{itemize}
\item Yosys AppNote 010: Converting Verilog to BLIF \dotfill Page \pageref{app:010} \hskip2cm\null
\item Yosys AppNote 011: Interactive Design Investigation \dotfill Page \pageref{app:011} \hskip2cm\null
\end{itemize}
\eject\label{app:010}
\includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_010_Verilog_to_BLIF.pdf}
\eject\label{app:011}
\includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_011_Design_Investigation.pdf}