mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
Using $pos models for $bu0
This commit is contained in:
parent
5733f4a39d
commit
b9cb483f3e
3 changed files with 3 additions and 18 deletions
|
@ -575,7 +575,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
|
|||
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
|
||||
{
|
||||
RTLIL::Const arg1_ext = arg1;
|
||||
extend(arg1_ext, result_len, signed1);
|
||||
extend_u0(arg1_ext, result_len, signed1);
|
||||
|
||||
return arg1_ext;
|
||||
}
|
||||
|
|
|
@ -470,7 +470,7 @@ struct SatGen
|
|||
{
|
||||
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
|
||||
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
|
||||
extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
|
||||
extendSignalWidthUnary(undef_a, undef_y, cell);
|
||||
|
||||
if (cell->type == "$pos" || cell->type == "$bu0") {
|
||||
ez->assume(ez->vec_eq(undef_a, undef_y));
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue