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test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.

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These parts keep rereading a Verilog module, then using chparam
to test it with various parameter combinations.  Since the default
parameters are on the large side, this spends a lot of time
needlessly elaborating the default parametrization that will then
be discarded.  Fix it with -deref and manual hierarchy call.

Shaves 30s off the test time on my machine.
This commit is contained in:
Marcelina Kościelnicka 2021-08-11 14:14:45 +02:00
parent 72d86c327e
commit b98376884e
2 changed files with 156 additions and 78 deletions
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81
tests/arch/ice40/memories.ys
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@ -1,86 +1,100 @@
# ================================ RAM ================================
# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
## With parameters
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:SB_RAM40_4K # too inefficient
select -assert-min 1 t:SB_DFFE
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K # any case works
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set ram_block 1 m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
select -assert-min 1 t:SB_DFFE
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set logic_block 1 m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
select -assert-min 1 t:SB_DFFE
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_romstyle "ebr" m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set rom_block 1 m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:$mem_v2 # requested BROM but this is a RAM
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
design -reset; read_verilog ../common/blockram.v
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set ram_block 1 m:memory
synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
@ -88,80 +102,93 @@ select -assert-count 1 t:$mem_v2 # requested BRAM but BRAM is disabled
# ================================ ROM ================================
# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
hierarchy -top sync_rom
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
hierarchy -top sync_rom
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
hierarchy -top sync_rom
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
## With parameters
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 0 t:SB_RAM40_4K # too inefficient
select -assert-min 1 t:SB_LUT4
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set rom_block 1 m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
select -assert-min 1 t:SB_LUT4
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set logic_block 1 m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
select -assert-min 1 t:SB_LUT4
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set syn_ramstyle "block_ram" m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set ram_block 1 m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:$mem_v2 # requested BRAM but this is a ROM
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
synth_ice40 -top sync_rom -nobram; cd sync_rom
select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled
design -reset; read_verilog ../common/blockrom.v
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set rom_block 1 m:memory
synth_ice40 -top sync_rom -nobram; cd sync_rom
select -assert-count 1 t:$mem_v2 # requested BROM but BRAM is disabled