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Work in progress for renaming labels/options in synth_xilinx

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This commit is contained in:
Eddie Hung 2019-07-18 14:20:43 -07:00
parent 9cb0456b6f
commit b97fe6e866
3 changed files with 17 additions and 14 deletions
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60
techlibs/xilinx/lutrams.txt Normal file
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@ -0,0 +1,60 @@
bram $__XILINX_RAM32X1D
init 1
abits 5
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
bram $__XILINX_RAM64X1D
init 1
abits 6
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
bram $__XILINX_RAM128X1D
init 1
abits 7
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 0
clocks 0 1
clkpol 0 2
endbram
match $__XILINX_RAM32X1D
min bits 3
min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM64X1D
min bits 5
min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
min bits 9
min wports 1
make_outreg
endmatch