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Automatically select new objects in abc and techmap passes

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This commit is contained in:
Clifford Wolf 2013-03-08 09:16:25 +01:00
parent 79b3afa011
commit b96ffed69b
3 changed files with 19 additions and 1 deletions
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2
passes/techmap/techmap.cc
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@ -112,6 +112,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
w->port_output = false;
w->port_id = 0;
module->wires[w->name] = w;
design->select(module, w);
}
for (auto &it : tpl->cells) {
@ -122,6 +123,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
for (auto &it2 : c->connections)
apply_prefix(cell_name, it2.second, module);
module->cells[c->name] = c;
design->select(module, c);
}
for (auto &it : tpl->connections) {