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Automatically select new objects in abc and techmap passes

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This commit is contained in:
Clifford Wolf 2013-03-08 09:16:25 +01:00
parent 79b3afa011
commit b96ffed69b
3 changed files with 19 additions and 1 deletions
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13
passes/opt/opt_rmunused.cc
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@ -118,6 +118,17 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
return w2->name < w1->name;
}
static bool check_public_name(RTLIL::IdString id)
{
if (id[0] == '$')
return false;
#if 0
if (id.find(".$") == std::string::npos)
return true;
#endif
return false;
}
static void rmunused_module_signals(RTLIL::Module *module)
{
SigMap assign_map(module);
@ -157,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module)
std::vector<RTLIL::Wire*> del_wires;
for (auto &it : module->wires) {
RTLIL::Wire *wire = it.second;
if (wire->name[0] == '\\') {
if (check_public_name(wire->name)) {
RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1;
assign_map.apply(s2);
if (!used_signals.check_any(s2) && wire->port_id == 0) {