mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

abc9_ops: fix -reintegrate handling of $__ABC9_DELAY

Browse source
This commit is contained in:
Eddie Hung 2020-01-14 14:06:02 -08:00
parent ec95fbb273
commit b951ca9e1c
1 changed files with 3 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/techmap/abc9_ops.cc
View file

@ -659,7 +659,7 @@ void reintegrate(RTLIL::Module *module)
bit_drivers[i].insert(mapped_cell->name);
}
}
else if (mapped_cell->type == ID($__ABC9_DELAY)) {
else if (box_lookup.at(mapped_cell->type, IdString()) == ID($__ABC9_DELAY)) {
SigBit I = mapped_cell->getPort(ID(i));
SigBit O = mapped_cell->getPort(ID(o));
if (I.wire)
@ -671,7 +671,8 @@ void reintegrate(RTLIL::Module *module)
}
else {
RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
log_assert(existing_cell);
if (!existing_cell)
log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
log_assert(mapped_cell->type.begins_with("$__boxid"));
auto type = box_lookup.at(mapped_cell->type, IdString());