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	read_aiger: connect identical signals together
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			@ -280,6 +280,7 @@ end_of_header:
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				if (wire) {
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					// Could have been renamed by a latch
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					module->swap_names(wire, outputs[l1]);
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					module->connect(outputs[l1], wire);
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					goto next;
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				}
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				wire = outputs[l1];
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