Merge branch 'YosysHQ:main' into master

.github/ISSUE_TEMPLATE/bug_report.yml

@@ -6,6 +6,8 @@ body:
     attributes:
       value: >
 
+        Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html#reporting-bugs) about how to report bugs. We fix well-reported bugs the fastest.
+
         If you have a general question, please ask it on the [Discourse forum](https://yosyshq.discourse.group/).
 
 

CHANGELOG

@@ -2,9 +2,30 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.61 .. Yosys 0.62-dev
+Yosys 0.62 .. Yosys 0.63-dev
 --------------------------
 
+Yosys 0.61 .. Yosys 0.62
+--------------------------
+ * Various
+    - verific: Added "-sv2017" flag option to support System
+      Verilog 2017.
+    - verific: Added VHDL related flags to "-f" and "-F" and
+      support reading VHDL file from file lists.
+    - Updated cell libs with proper module declaration where
+      non standard (...) style was used.
+
+ * New commands and options
+    - Added "-word" option to "lut2mux" pass to enable emitting
+      word level cells.
+    - Added experimental "opt_balance_tree" pass to convert
+      cascaded cells into tree of cells to improve timing.
+    - Added "-gatesi" option to "write_blif" pass to init gates
+      under gates_mode in BLIF format.
+    - Added "-on" and "-off" options to "debug" pass for 
+      persistent debug logging.
+    - Added "linux_perf" pass to control performance recording.
+
 Yosys 0.60 .. Yosys 0.61
 --------------------------
  * Various

CONTRIBUTING.md

@@ -1,70 +1,63 @@
-# Introduction
+# Contributing to Yosys
 
-Thanks for thinking about contributing to the Yosys project.  If this is your
+Thanks for considering helping out. If this is your
 first time contributing to an open source project, please take a look at the
-following guide:
+following guide about the basics:
 https://opensource.guide/how-to-contribute/#orienting-yourself-to-a-new-project.
 
-Information about the Yosys coding style is available on our Read the Docs:
-https://yosys.readthedocs.io/en/latest/yosys_internals/extending_yosys/contributing.html.
+## Asking questions
 
-# Using the issue tracker
-
-The [issue tracker](https://github.com/YosysHQ/yosys/issues) is used for
-tracking bugs or other problems with Yosys or its documentation.  It is also the
-place to go for requesting new features.
-When [creating a new issue](https://github.com/YosysHQ/yosys/issues/new/choose),
-we have a few templates available.  Please make use of these!  It will make it
-much easier for someone to respond and help.
-
-### Bug reports
-
-Before you submit an issue, please check out the [how-to guide for
-`bugpoint`](https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html).
-This guide will take you through the process of using the [`bugpoint`
-command](https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html) in Yosys to
-produce a [minimal, complete and verifiable
-example](https://stackoverflow.com/help/minimal-reproducible-example) (MVCE).
-Providing an MVCE with your bug report drastically increases the likelihood that
-someone will be able to help resolve your issue.
-
-
-# Using pull requests
-
-If you are working on something to add to Yosys, or fix something that isn't
-working quite right, make a [PR](https://github.com/YosysHQ/yosys/pulls)!  An
-open PR, even as a draft, tells everyone that you're working on it and they
-don't have to.  It can also be a useful way to solicit feedback on in-progress
-changes.  See below to find the best way to [ask us
-questions](#asking-questions).
-
-In general, all changes to the code are done as a PR, with [Continuous
-Integration (CI)](https://github.com/YosysHQ/yosys/actions) tools that
-automatically run the full suite of tests compiling and running Yosys.  Please
-make use of this!  If you're adding a feature: add a test!  Not only does it
-verify that your feature is working as expected, but it can also be a handy way
-for people to see how the feature is used.  If you're fixing a bug: add a test!
-If you can, do this first; it's okay if the test starts off failing - you
-already know there is a bug.  CI also helps to make sure that your changes still
-work under a range of compilers, settings, and targets.
-
-
-### Labels
-
-We use [labels](https://github.com/YosysHQ/yosys/labels) to help categorise
-issues and PRs.  If a label seems relevant to your work, please do add it; this
-also includes the labels beggining with 'status-'.  The 'merge-' labels are used
-by maintainers for tracking and communicating which PRs are ready and pending
-merge; please do not use these labels if you are not a maintainer.
-
-
-# Asking questions
-
-If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/) or in our [discussions
-page](https://github.com/YosysHQ/yosys/discussions).
+If you have a question about how to use Yosys, please ask on our [Discourse forum](https://yosyshq.discourse.group/).
 The Discourse is also a great place to ask questions about developing or
 contributing to Yosys.
 
 We have open [dev 'jour fixe' (JF) meetings](https://docs.google.com/document/d/1SapA6QAsJcsgwsdKJDgnGR2mr97pJjV4eeXg_TVJhRU/edit?usp=sharing) where developers from YosysHQ and the
 community come together to discuss open issues and PRs.  This is also a good
 place to talk to us about how to implement larger PRs.
+
+## Using the issue tracker
+
+The [issue tracker](https://github.com/YosysHQ/yosys/issues) is used for
+tracking bugs or other problems with Yosys or its documentation.  It is also the
+place to go for requesting new features.
+
+### Bug reports
+
+Learn more [here](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/contributing.html#reporting-bugs) about how to report bugs. We fix well-reported bugs the fastest.
+
+## Contributing code
+
+If you're adding complex functionality, or modifying core parts of Yosys,
+we highly recommend discussing your motivation and approach
+ahead of time on the [Discourse forum](https://yosyshq.discourse.group/).
+
+### Using pull requests
+
+If you are working on something to add to Yosys, or fix something that isn't
+working quite right,
+make a [pull request (PR)](https://github.com/YosysHQ/yosys/pulls).
+
+An open PR, even as a draft, tells everyone that you're working on it and they
+don't have to. It can also be a useful way to solicit feedback on in-progress
+changes. See above to find the best way to [ask us questions](#asking-questions).
+
+### Continuous integration
+
+[Continuous Integration (CI)](https://github.com/YosysHQ/yosys/actions) tools
+automatically compile Yosys and run it with the full suite of tests.
+If you're a first time contributor, a maintainer has to trigger a run for you.
+We test on various platforms, compilers. Sanitizer builds are only tested
+on the main branch.
+
+### Labels
+
+We use [labels](https://github.com/YosysHQ/yosys/labels) to help categorise
+issues and PRs.  If a label seems relevant to your work, please do add it; this
+also includes the labels beginning with 'status-'.  The 'merge-' labels are used
+by maintainers for tracking and communicating which PRs are ready and pending
+merge; please do not use these labels if you are not a maintainer.
+
+
+### Coding style
+
+Learn more [here](https://yosys.readthedocs.io/en/latest/yosys_internals/extending_yosys/contributing.html).

Makefile

@@ -161,7 +161,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.61+0
+YOSYS_VER := 0.62+9
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)
@@ -186,7 +186,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 5ae48ee.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 7326bb7.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 

README.md

@@ -246,6 +246,8 @@ Building the documentation
 
 Note that there is no need to build the manual if you just want to read it.
 Simply visit https://yosys.readthedocs.io/en/latest/ instead.
+If you're offline, you can read the sources, replacing `.../en/latest`
+with `docs/source`.
 
 In addition to those packages listed above for building Yosys from source, the
 following are used for building the website:

abc

@@ -1 +1 @@
-Subproject commit 799ba632239b2a4db2bacda81de4e6efdc486b0c
+Subproject commit 734f64d5b907158dc4337ee82b3b74566d74ba08

backends/blif/blif.cc

@@ -44,6 +44,7 @@ struct BlifDumperConfig
 	bool iattr_mode;
 	bool blackbox_mode;
 	bool noalias_mode;
+	bool gatesi_mode;
 
 	std::string buf_type, buf_in, buf_out;
 	std::map<RTLIL::IdString, std::pair<RTLIL::IdString, RTLIL::IdString>> unbuf_types;
@@ -51,7 +52,7 @@ struct BlifDumperConfig
 
 	BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false),
 			cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false),
-			blackbox_mode(false), noalias_mode(false) { }
+			blackbox_mode(false), noalias_mode(false), gatesi_mode(false) { }
 };
 
 struct BlifDumper
@@ -118,16 +119,21 @@ struct BlifDumper
 		return str;
 	}
 
-	const std::string str_init(RTLIL::SigBit sig)
+	template <bool Space = true> const std::string str_init(RTLIL::SigBit sig)
 	{
 		sigmap.apply(sig);
 
-		if (init_bits.count(sig) == 0)
-			return " 2";
+		if (init_bits.count(sig) == 0) {
+			if constexpr (Space)
+				return " 2";
+			else
+				return "2";
+		}
 
-		string str = stringf(" %d", init_bits.at(sig));
-
-		return str;
+		if constexpr (Space)
+			return stringf(" %d", init_bits.at(sig));
+		else
+			return stringf("%d", init_bits.at(sig));
 	}
 
 	const char *subckt_or_gate(std::string cell_type)
@@ -469,6 +475,11 @@ struct BlifDumper
 				f << stringf(".names %s %s\n1 1\n", str(rhs_bit), str(lhs_bit));
 		}
 
+		if (config->gatesi_mode) {
+			for (auto &&init_bit : init_bits)
+				f << stringf(".gateinit %s=%s\n", str(init_bit.first), str_init<false>(init_bit.first));
+		}
+
 		f << stringf(".end\n");
 	}
 
@@ -550,6 +561,9 @@ struct BlifBackend : public Backend {
 		log("    -impltf\n");
 		log("        do not write definitions for the $true, $false and $undef wires.\n");
 		log("\n");
+		log("    -gatesi\n");
+		log("        write initial bit(s) with .gateinit for gates that needs to be initialized.\n");
+		log("\n");
 	}
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
 	{
@@ -640,6 +654,10 @@ struct BlifBackend : public Backend {
 				config.noalias_mode = true;
 				continue;
 			}
+			if (args[argidx] == "-gatesi") {
+				config.gatesi_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);

docs/source/code_examples/macro_commands/prep.ys

@@ -17,6 +17,7 @@ coarse:
     opt_clean
     memory_collect
     opt -noff -keepdc -fast
+    sort
 
 check:
     stat

docs/source/conf.py

@@ -6,7 +6,7 @@ import os
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2026 YosysHQ GmbH'
-yosys_ver = "0.61"
+yosys_ver = "0.62"
 
 # select HTML theme
 html_theme = 'furo-ys'

docs/source/using_yosys/verilog.rst

@@ -355,6 +355,9 @@ from SystemVerilog:
   design with `read_verilog`, all its packages are available to SystemVerilog
   files being read into the same design afterwards.
 
+  - nested packages are currently not supported (i.e. calling ``import`` inside
+    a ``package`` .. ``endpackage`` block)
+
 - typedefs are supported (including inside packages)
 
   - type casts are currently not supported

docs/source/yosys_internals/extending_yosys/contributing.rst

@@ -1,57 +1,16 @@
 Contributing to Yosys
 =====================
 
-.. note::
-
-   For information on making a pull request on github, refer to our
-   |CONTRIBUTING|_ file.
-
-.. |CONTRIBUTING| replace:: :file:`CONTRIBUTING.md`
-.. _CONTRIBUTING: https://github.com/YosysHQ/yosys/blob/main/CONTRIBUTING.md
-
-Coding Style
-------------
-
-Formatting of code
-~~~~~~~~~~~~~~~~~~
-
-- Yosys code is using tabs for indentation. Tabs are 8 characters.
-
-- A continuation of a statement in the following line is indented by two
-  additional tabs.
-
-- Lines are as long as you want them to be. A good rule of thumb is to break
-  lines at about column 150.
-
-- Opening braces can be put on the same or next line as the statement opening
-  the block (if, switch, for, while, do). Put the opening brace on its own line
-  for larger blocks, especially blocks that contains blank lines.
-
-- Otherwise stick to the `Linux Kernel Coding Style`_.
-
-.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst
-
-
-C++ Language
-~~~~~~~~~~~~
-
-Yosys is written in C++17.
-
-In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings
-for implicit type casts, always use ``GetSize(foobar)`` instead of
-``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`)
-
-Use range-based for loops whenever applicable.
-
-
 Reporting bugs
 --------------
 
-- use the `bug report template`_
+A good bug report includes the following information:
 
-.. _bug report template: https://github.com/YosysHQ/yosys/issues/new?template=bug_report.yml
 
-- short title briefly describing the issue, e.g.
+Title
+~~~~~
+
+briefly describe the issue, for example:
 
    techmap of wide mux with undefined inputs raises error during synth_xilinx
 
@@ -64,10 +23,18 @@ Reporting bugs
 Reproduction Steps
 ~~~~~~~~~~~~~~~~~~
 
-- ideally a code-block (starting and ending with triple backquotes) containing
-  the minimized design (Verilog or RTLIL), followed by a code-block containing
-  the minimized yosys script OR a command line call to yosys with
-  code-formatting (starting and ending with single backquotes)
+The reproduction steps should be a minimal, complete and verifiable
+example `MVCE`_.
+Providing an MVCE with your bug report drastically increases the likelihood that
+someone will be able to help resolve your issue.
+One way to minimize a design is to use the `bugpoint_` command.
+You can learn more in the `how-to guide for bugpoint_`.
+
+The reproduction steps are ideally a code-block (starting and ending with
+triple backquotes) containing
+the minimized design (Verilog or RTLIL), followed by a code-block containing
+the minimized yosys script OR a command line call to yosys with
+code-formatting (starting and ending with single backquotes).
 
 .. code-block:: markdown
 
@@ -86,9 +53,9 @@ Reproduction Steps
 
    `yosys -p ': minimum sequence of commands;' min.v`
 
-- alternatively can provide a single code-block which includes the minimized
-  design as a "here document" followed by the sequence of commands which
-  reproduce the error
+Alternatively, you can provide a single code-block which includes the minimized
+design as a "here document" followed by the sequence of commands which
+reproduce the error
 
   + see :doc:`/using_yosys/more_scripting/load_design` for more on heredocs.
 
@@ -101,7 +68,9 @@ Reproduction Steps
    # minimum sequence of commands
    ```
 
-- any environment variables or command line options should also be mentioned
+Don't forget to mention:
+
+- any important environment variables or command line options
 - if the problem occurs for a range of values/designs, what is that range
 - if you're using an external tool, such as ``valgrind``, to detect the issue,
   what version of that tool are you using and what options are you giving it
@@ -115,46 +84,58 @@ Reproduction Steps
    around Yosys such as OpenLane; you should instead minimize your input and
    reproduction steps to just the Yosys part.
 
-"Expected Behaviour"
-~~~~~~~~~~~~~~~~~~~~
+.. _MVCE: https://stackoverflow.com/help/minimal-reproducible-example
+.. _bugpoint: https://yosys.readthedocs.io/en/latest/cmd/bugpoint.html
+.. _how-to guide for bugpoint: https://yosys.readthedocs.io/en/latest/using_yosys/bugpoint.html
 
-- if you have a similar design/script that doesn't give the error, include it
-  here as a reference
-- if the bug is that an error *should* be raised but isn't, are there any other
-  commands with similar error messages
-
-
-"Actual Behaviour"
+Expected Behaviour
 ~~~~~~~~~~~~~~~~~~
 
-- any error messages go here
-- any details relevant to the crash that were found with ``--trace`` or
-  ``--debug`` flags
-- if you identified the point of failure in the source code, you could mention
-  it here, or as a comment below
+Describe what you'd expect to happen when we follow the reproduction steps
+if the bug was fixed.
 
-  + if possible, use a permalink to the source on GitHub
-  + you can browse the source repository for a certain commit with the failure
+If you have a similar design/script that doesn't give the error, include it
+here as a reference. If the bug is that an error *should* be raised but isn't,
+note if there are any other commands with similar error messages.
+
+
+Actual Behaviour
+~~~~~~~~~~~~~~~~
+
+Describe what you actually see when you follow the reproduction steps.
+
+This can include:
+
+* any error messages
+* any details relevant to the crash that were found with ``--trace`` or
+  ``--debug`` flags
+* the part of the source code that triggers the bug
+
+  * if possible, use a permalink to the source on GitHub
+  * you can browse the source repository for a certain commit with the failure
     and open the source file, select the relevant lines (click on the line
     number for the first relevant line, then while holding shift click on the
     line number for the last relevant line), click on the ``...`` that appears
     and select "Copy permalink"
-  + should look something like
+  * should look something like
     ``https://github.com/YosysHQ/yosys/blob/<commit_hash>/path/to/file#L139-L147``
-  + clicking on "Preview" should reveal a code block containing the lines of
+  * clicking on "Preview" should reveal a code block containing the lines of
     source specified, with a link to the source file at the given commit
 
 
-Additional details
+Additional Details
 ~~~~~~~~~~~~~~~~~~
 
-- once you have created the issue, any additional details can be added as a
-  comment on that issue
-- could include any additional context as to what you were doing when you first
-  encountered the bug
-- was this issue discovered through the use of a fuzzer
-- if you've minimized the script, consider including the `bugpoint` script you
-  used, or the original script, e.g.
+Anything else you think might be helpful or relevant when verifying or fixing
+the bug.
+
+Once you have created the issue, any additional details can be added as a
+comment on that issue. You can include any additional context as to what you
+were doing when you first encountered the bug.
+
+If this issue discovered through the use of a fuzzer, ALWAYS declare that.
+If you've minimized the script, consider including the `bugpoint` script you
+used, or the original script, for example:
 
 .. code-block:: markdown
 
@@ -171,8 +152,226 @@ Additional details
    Minimized from
    `yosys -p ': original sequence of commands to produce error;' design.v`
 
-- if you're able to, it may also help to share the original un-minimized design
-
-  + if the design is too big for a comment, consider turning it into a `Gist`_
+If possible, it may also help to share the original un-minimized design.
+If the design is too big for a comment, consider turning it into a `Gist`_
 
 .. _Gist: https://gist.github.com/
+
+Contributing code
+-----------------
+
+Code that matters
+~~~~~~~~~~~~~~~~~
+
+If you're adding complex functionality, or modifying core parts of yosys,
+we highly recommend discussing your motivation and approach
+ahead of time on the `Discourse forum`_. Please, be as explicit and concrete
+as possible when explaining the motivation for what you're building.
+Additionally, if you do so on the forum first before you starting hacking
+away at C++, you might solve your problem without writing a single line
+of code!
+
+PRs are considered for relevance, priority, and quality
+based on their descriptions first, code second.
+
+Before you build or fix something, also search for existing `issues`_.
+
+.. _`Discourse forum`: https://yosyshq.discourse.group/
+.. _`issues`: https://github.com/YosysHQ/yosys/issues
+
+Making sense
+~~~~~~~~~~~~
+
+Given enough effort, the behavior of any code can be figured out to any
+desired extent. However, the author of the code is by far in the best
+position to make this as easy as possible.
+
+Yosys is a long-standing project and has accumulated a lot of C-style code
+that's not written to be read, just written to run. We improve this bit
+by bit when opportunities arise, but it is what it is.
+New additions are expected to be a lot cleaner.
+
+The purpose and behavior of the code changed should be described clearly.
+Your change should contain exactly what it needs to match that description.
+This means:
+
+* nothing more than that - no dead code, no undocumented features
+* nothing missing - if something is partially built, that's fine,
+  but you have to make that clear. For example, some passes
+  only support some types of cells
+
+Here are some software engineering approaches that help:
+
+* Use abstraction to model the problem and hide details
+
+  * Maximize the usage of types (structs over loose variables),
+    not necessarily in an object-oriented way
+  * Use functions, scopes, type aliases
+
+* In new passes, make sure the logic behind how and why it works is actually provided
+  in coherent comments, and that variable and type naming is consistent with the terms
+  you use in the description.
+* The logic of the implementation should be described in mathematical
+  or algorithm theory terms. Correctness, termination, computational complexity.
+  Make it clear if you're re-implementing a classic data structure for logic synthesis
+  or graph traversal etc.
+
+* There's various ways of traversing the design with use-def indices (for getting
+  drivers and driven signals) available in Yosys. They have advantages and sometimes
+  disadvantages. Prefer not re-implementing these
+* Prefer references over pointers, and smart pointers over raw pointers
+* Aggressively deduplicate code. Within functions, within passes,
+  across passes, even against existing code
+* Prefer declaring things ``const``
+* Prefer range-based for loops over C-style
+
+Common mistakes
+~~~~~~~~~~~~~~~
+
+* Deleting design objects invalidates iterators. Defer deletions or hold a copy
+  of the list of pointers to design objects
+* Deleting wires can get sketchy and is intended to be done solely by
+  the ``opt_clean`` pass so just don't do it
+* Iterating over an entire design and checking if things are selected is more
+  inefficient than using the ``selected_*`` methods
+* Remember to call ``fixup_ports`` at the end if you're modifying module interfaces
+
+Testing your change
+~~~~~~~~~~~~~~~~~~~
+
+Untested code can't be maintained. Inevitable codebase-wide changes
+are likely to break anything untested. Tests also help reviewers understand
+the purpose of the code change in practice.
+
+Your code needs to come with tests. If it's a feature, a test that covers
+representative examples of the added behavior. If it's a bug fix, it should
+reproduce the original isolated bug. But in some situations, adding a test
+isn't viable. If you can't provide a test, explain this decision.
+
+Prefer writing unit tests (:file:`tests/unit`) for isolated tests to
+the internals of more serious code changes, like those to the core of yosys,
+or more algorithmic ones.
+
+The rest of the test suite is mostly based on running Yosys on various Yosys
+and Tcl scripts that manually call Yosys commands.
+See :doc:`/yosys_internals/extending_yosys/test_suites` for more information
+about how our test suite is structured.
+The basic test writing approach is checking
+for the presence of some kind of object or pattern with ``-assert-count`` in
+:doc:`/using_yosys/more_scripting/selections`.
+
+It's often best to use equivalence checking with ``equiv_opt -assert``
+or similar to prove that the changes done to the design by a modified pass
+preserve equivalence. But some code isn't meant to preserve equivalence.
+Sometimes proving equivalence takes an impractically long time for larger
+inputs. Also beware, the ``equiv_`` passes are a bit quirky and might even
+have incorrect results in unusual situations.
+
+.. Changes to core parts of Yosys or passes that are included in synthesis flows
+.. can change runtime and memory usage - for the better or for worse. This strongly
+.. depends on the design involved. Such risky changes should then be benchmarked
+.. with various designs.
+
+.. TODO Emil benchmarking
+
+Coding style
+~~~~~~~~~~~~
+
+Yosys is written in C++17.
+
+In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings
+for implicit type casts, always use ``GetSize(foobar)`` instead of
+``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`)
+
+For auto formatting code, a :file:`.clang-format` file is present top-level.
+Yosys code is using tabs for indentation. A tab is 8 characters wide,
+but prefer not relying on it. A continuation of a statement
+in the following line is indented by two additional tabs. Lines are
+as long as you want them to be. A good rule of thumb is to break lines
+at about column 150. Opening braces can be put on the same or next line
+as the statement opening the block (if, switch, for, while, do).
+Put the opening brace on its own line for larger blocks, especially
+blocks that contains blank lines. Remove trailing whitespace on sight.
+
+Otherwise stick to the `Linux Kernel Coding Style`_.
+
+.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst
+
+Git style
+~~~~~~~~~
+
+We don't have a strict commit message style.
+
+Some style hints:
+
+* Refactor and document existing code if you touch it,
+  but in separate commits from your functional changes
+* Prefer smaller commits organized by good chunks. Git has a lot of features
+  like fixup commits, interactive rebase with autosquash
+
+Reviewing PRs
+-------------
+
+Reviewing PRs is a totally valid form of external contributing to the project!
+
+Who's the reviewer?
+~~~~~~~~~~~~~~~~~~~
+
+Yosys HQ is a company with the inherited mandate to make decisions on behalf
+of the open source project. As such, we at HQ are collectively the maintainers.
+Within HQ, we allocate reviews based on expertise with the topic at hand
+as well as member time constraints.
+
+If you're intimately acquainted with a part of the codebase, we will be happy
+to defer to your experience and have you review PRs. The official way we like
+is our CODEOWNERS file in the git repository. What we're looking for in code
+owners is activity and trust. For activity, if you're only interested in
+a yosys pass for example for the time you spend writing a thesis, it might be
+better to focus on writing good tests and docs in the PRs you submit rather than
+to commit to code ownership and therefore to be responsible for fixing things
+and reviewing other people's PRs at various unexpected points later. If you're
+prolific in some part of the codebase and not a code owner, we still value your
+experience and may tag you in PRs.
+
+As a matter of fact, the purpose of code ownership is to avoid maintainer
+burnout by removing orphaned parts of the codebase. If you become a code owner
+and stop being responsive, in the future, we might decide to remove such code
+if convenient and costly to maintain. It's simply more respectful of the users'
+time to explicitly cut something out than let it "bitrot". Larger projects like
+LLVM or linux could not survive without such things, but Yosys is far smaller,
+and there are expectations
+
+.. TODO this deserves its own section elsewhere I think? But it would be distracting elsewhere
+
+Sometimes, multiple maintainers may add review comments. This is considered
+healthy collaborative even if it might create disagreement at times. If
+somebody is already reviewing a PR, others, even non-maintainers are free to
+leave comments with extra observations and alternate perspectives in a
+collaborative spirit.
+
+How to review
+~~~~~~~~~~~~~
+
+First, read everything above about contributing. Those are the values you
+should gently enforce as a reviewer. They're ordered by importance, but
+explicitly, descriptions are more important than code, long-form comments
+describing the design are more important than piecemeal comments, etc.
+
+If a PR is poorly described, incomplete, tests are broken, or if the
+author is not responding, please don't feel pressured to take over their
+role by reverse engineering the code or fixing things for them, unless
+there are good reasons to do so.
+
+If a PR author submits LLM outputs they haven't understood themselves,
+they will not be able to implement feedback. Take this into consideration
+as well. We do not ban LLM code from the codebase, we ban bad code.
+
+Reviewers may have diverse styles of communication while reviewing - one
+may do one thorough review, another may prefer a back and forth with the
+basics out the way before digging into the code. Generally, PRs may have
+several requests for modifications and long discussions, but often
+they just are good enough to merge as-is.
+
+The CI is required to go green for merging. New contributors need a CI
+run to be triggered by a maintainer before their PRs take up computing
+resources. It's a single click from the github web interface.

frontends/ast/genrtlil.cc

@@ -2085,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			check_unique_id(current_module, id, this, "cell");
 			RTLIL::Cell *cell = current_module->addCell(id, "");
 			set_src_attr(cell, this);
-			// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
-			cell->set_bool_attribute(ID::module_not_derived);
 
 			for (auto it = children.begin(); it != children.end(); it++) {
 				auto* child = it->get();
@@ -2149,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				}
 				log_abort();
 			}
+
+			// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
+			if (cell->type.isPublic())
+				cell->set_bool_attribute(ID::module_not_derived);
+
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
 					input_error("Attribute `%s' with non-constant value.\n", attr.first);

frontends/blif/blifparse.cc

@@ -470,6 +470,27 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
 				continue;
 			}
 
+			if (!strcmp(cmd, ".gateinit"))
+			{
+				char *p = strtok(NULL, " \t\r\n");
+				if (p == NULL)
+					goto error;
+
+				char *n = strtok(p, "=");
+				char *init = strtok(NULL, "=");
+				if (n == NULL || init == NULL)
+					goto error;
+				if (init[0] != '0' && init[0] != '1')
+					goto error;
+
+				if (blif_wire(n)->attributes.find(ID::init) == blif_wire(n)->attributes.end())
+					blif_wire(n)->attributes.emplace(ID::init, Const(init[0] == '1' ? 1 : 0, 1));
+				else
+					blif_wire(n)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
+
+				continue;
+			}
+
 			if (!strcmp(cmd, ".names"))
 			{
 				char *p;

frontends/verific/verific.cc

@@ -3114,9 +3114,11 @@ struct VerificPass : public Pass {
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
-		log("    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
+		log("    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|\n");
+		log("             -sv2017|-sv} <verilog-file>..\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog files into Verific.\n");
+		log("Note that -sv option will use latest supported SystemVerilog standard.\n");
 		log("\n");
 		log("All files specified in one call to this command are one compilation unit.\n");
 		log("Files passed to different calls to this command are treated as belonging to\n");
@@ -3161,7 +3163,10 @@ struct VerificPass : public Pass {
 #endif
 #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
 		log("    verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n");
-		log("                     -sv2012|-sv|-formal] <command-file>\n");
+#ifdef VERIFIC_VHDL_SUPPORT
+		log("                     -vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl|\n");
+#endif
+		log("                     -sv2012|-sv2017|-sv|-formal] <command-file>\n");
 		log("\n");
 		log("Load and execute the specified command file.\n");
 		log("Override verilog parsing mode can be set.\n");
@@ -3696,6 +3701,9 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
 		{
 			unsigned verilog_mode = veri_file::UNDEFINED;
+#ifdef VERIFIC_VHDL_SUPPORT
+			unsigned vhdl_mode = vhdl_file::UNDEFINED;
+#endif
 			bool is_formal = false;
 			const char* filename = nullptr;
 
@@ -3714,10 +3722,38 @@ struct VerificPass : public Pass {
 				} else if (args[argidx] == "-sv2009") {
 					verilog_mode = veri_file::SYSTEM_VERILOG_2009;
 					continue;
-				} else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal") {
+				} else if (args[argidx] == "-sv2012") {
+					verilog_mode = veri_file::SYSTEM_VERILOG_2012;
+					continue;
+				} else if (args[argidx] == "-sv2017") {
+					verilog_mode = veri_file::SYSTEM_VERILOG_2017;
+					continue;
+				} else if (args[argidx] == "-sv" || args[argidx] == "-formal") {
 					verilog_mode = veri_file::SYSTEM_VERILOG;
 					if (args[argidx] == "-formal") is_formal = true;
 					continue;
+#ifdef VERIFIC_VHDL_SUPPORT
+				} else if (args[argidx] == "-vhdl87") {
+					vhdl_mode = vhdl_file::VHDL_87;
+					vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
+					continue;
+				} else if (args[argidx] == "-vhdl93") {
+					vhdl_mode = vhdl_file::VHDL_93;
+					vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
+					continue;
+				} else if (args[argidx] == "-vhdl2k") {
+					vhdl_mode = vhdl_file::VHDL_2K;
+					vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
+					continue;
+				} else if (args[argidx] == "-vhdl2019") {
+					vhdl_mode = vhdl_file::VHDL_2019;
+					vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str());
+					continue;
+				} else if (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl") {
+					vhdl_mode = vhdl_file::VHDL_2008;
+					vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
+					continue;
+#endif
 				} else if (args[argidx].compare(0, 1, "-") == 0) {
 					cmd_error(args, argidx, "unknown option");
 					goto check_error;
@@ -3742,10 +3778,36 @@ struct VerificPass : public Pass {
 			veri_file::DefineMacro("VERIFIC");
 			veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
 
+#ifdef VERIFIC_VHDL_SUPPORT
+			if (vhdl_mode == vhdl_file::UNDEFINED) {
+				vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
+				vhdl_mode = vhdl_file::VHDL_2008;
+			}
+			int i;
+			Array *file_names_sv = new Array(POINTER_HASH);
+			FOREACH_ARRAY_ITEM(file_names, i, filename) {
+				std::string filename_str = filename;
+				if ((filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") ||
+						(filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl")) {
+					if (!vhdl_file::Analyze(filename, work.c_str(), vhdl_mode)) {
+						verific_error_msg.clear();
+						log_cmd_error("Reading VHDL sources failed.\n");
+					}
+				} else {
+					file_names_sv->Insert(strdup(filename));
+				}
+			}
+			if (!veri_file::AnalyzeMultipleFiles(file_names_sv, analysis_mode, work.c_str(), veri_file::MFCU)) {
+				verific_error_msg.clear();
+				log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
+			}
+			delete file_names_sv;
+#else
 			if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {
 				verific_error_msg.clear();
 				log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 			}
+#endif
 
 			delete file_names;
 			verific_import_pending = true;
@@ -3753,7 +3815,8 @@ struct VerificPass : public Pass {
 		}
 
 		if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
-				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
+				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv2017" || args[argidx] == "-sv" ||
+				args[argidx] == "-formal"))
 		{
 			Array file_names;
 			unsigned verilog_mode;
@@ -3766,7 +3829,11 @@ struct VerificPass : public Pass {
 				verilog_mode = veri_file::SYSTEM_VERILOG_2005;
 			else if (args[argidx] == "-sv2009")
 				verilog_mode = veri_file::SYSTEM_VERILOG_2009;
-			else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")
+			else if (args[argidx] == "-sv2012")
+				verilog_mode = veri_file::SYSTEM_VERILOG_2012;
+			else if (args[argidx] == "-sv2017")
+				verilog_mode = veri_file::SYSTEM_VERILOG_2017;
+			else if (args[argidx] == "-sv" || args[argidx] == "-formal")
 				verilog_mode = veri_file::SYSTEM_VERILOG;
 			else
 				log_abort();

kernel/consteval.h

@@ -27,6 +27,10 @@
 
 YOSYS_NAMESPACE_BEGIN
 
+/**
+ * ConstEval provides on-demand constant propagation by traversing input cones
+ * with caching
+ */
 struct ConstEval
 {
 	RTLIL::Module *module;

kernel/log_help.cc

@@ -78,7 +78,7 @@ ContentListing* ContentListing::open_option(const string &text,
 }
 
 #define MAX_LINE_LEN 80
-void log_pass_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false) {
+void log_body_str(const std::string &pass_str, std::string indent_str, bool leading_newline=false, bool is_formatted=false) {
 	if (pass_str.empty())
 		return;
 	std::istringstream iss(pass_str);
@@ -86,26 +86,30 @@ void log_pass_str(const std::string &pass_str, std::string indent_str, bool lead
 		log("\n");
 	for (std::string line; std::getline(iss, line);) {
 		log("%s", indent_str);
-		auto curr_len = indent_str.length();
-		std::istringstream lss(line);
-		for (std::string word; std::getline(lss, word, ' ');) {
-			while (word[0] == '`' && word.back() == '`')
-				word = word.substr(1, word.length()-2);
-			if (curr_len + word.length() >= MAX_LINE_LEN-1) {
-				curr_len = 0;
-				log("\n%s", indent_str);
-			}
-			if (word.length()) {
-				log("%s ", word);
-				curr_len += word.length() + 1;
+		if (is_formatted) {
+			log("%s", line);
+		} else {
+			auto curr_len = indent_str.length();
+			std::istringstream lss(line);
+			for (std::string word; std::getline(lss, word, ' ');) {
+				while (word[0] == '`' && word.back() == '`')
+					word = word.substr(1, word.length()-2);
+				if (curr_len + word.length() >= MAX_LINE_LEN-1) {
+					curr_len = 0;
+					log("\n%s", indent_str);
+				}
+				if (word.length()) {
+					log("%s ", word);
+					curr_len += word.length() + 1;
+				}
 			}
 		}
 		log("\n");
 	}
 }
-void log_pass_str(const std::string &pass_str, int indent=0, bool leading_newline=false) {
+void log_body(const ContentListing &content, int indent=0, bool leading_newline=false) {
 	std::string indent_str(indent*4, ' ');
-	log_pass_str(pass_str, indent_str, leading_newline);
+	log_body_str(content.body, indent_str, leading_newline, content.type.compare("code") == 0);
 }
 
 PrettyHelp *current_help = nullptr;
@@ -134,16 +138,16 @@ void PrettyHelp::log_help() const
 {
 	for (auto &content : _root_listing) {
 		if (content.type.compare("usage") == 0) {
-			log_pass_str(content.body, 1, true);
+			log_body(content, 1, true);
 			log("\n");
 		} else if (content.type.compare("option") == 0) {
-			log_pass_str(content.body, 1);
+			log_body(content, 1);
 			for (auto text : content) {
-				log_pass_str(text.body, 2);
+				log_body(text, 2);
 				log("\n");
 			}
 		} else {
-			log_pass_str(content.body, 0);
+			log_body(content, 0);
 			log("\n");
 		}
 	}

kernel/pattern.h

@@ -0,0 +1,102 @@
+#ifndef OPT_DFF_COMP_H
+#define OPT_DFF_COMP_H
+
+#include "kernel/rtlil.h"
+#include <map>
+#include <optional>
+
+YOSYS_NAMESPACE_BEGIN
+
+/**
+ *  Pattern matching utilities for control signal analysis.
+ *
+ *  A pattern_t maps control signals to required values, representing a
+ *  product term (conjunction): {A=1, B=0} means "A AND !B".
+ *
+ *  A patterns_t is a set of patterns representing a sum-of-products:
+ *  {{A=1, B=0}, {A=0, C=1}} means "(A AND !B) OR (!A AND C)".
+ *
+ *  Used for analyzing MUX tree control paths in DFF optimization.
+ */
+
+// Pattern matching for clock enable
+// A pattern maps control signals to their required values for a MUX path
+typedef std::map<RTLIL::SigBit, bool> pattern_t; // Set of control signals that must ALL match required vals
+typedef std::set<pattern_t> patterns_t;          // Alternative patterns (OR)
+typedef std::pair<RTLIL::SigBit, bool> ctrl_t;   // Control signal
+typedef std::set<ctrl_t> ctrls_t;                // Set of control signals that must ALL be active
+
+/**
+ * Find if two patterns differ in exactly one variable.
+ * Example: {A=1,B=1} vs {A=1,B=0} returns B, allows simplification: (A&B) | (A&!B) => A
+ */
+inline std::optional<RTLIL::SigBit> find_complementary_pattern_var(
+	const pattern_t& left,
+	const pattern_t& right
+) {
+	std::optional<RTLIL::SigBit> ret;
+	for (const auto &pt : left) {
+		// Left requires signal that right doesn't constrain - incompatible domains
+		if (right.count(pt.first) == 0)
+			return std::nullopt;
+		// Signal has same required value in both - not the complement variable
+		if (right.at(pt.first) == pt.second)
+			continue;
+		// Already found one differing signal, now found another - not simplifiable
+		if (ret)
+			return std::nullopt;
+		// First differing signal - candidate complement variable
+		ret = pt.first;
+	}
+	return ret;
+}
+
+/**
+ * Simplify a sum-of-products by merging complementary patterns: (A&B) | (A&!B) => A,
+ * and removing redundant patterns: A | (A&B) => A
+ */
+inline void simplify_patterns(patterns_t& patterns) {
+	auto new_patterns = patterns;
+
+	// Merge complementary patterns
+	bool optimized;
+	do {
+		optimized = false;
+		for (auto i = patterns.begin(); i != patterns.end(); i++) {
+			for (auto j = std::next(i, 1); j != patterns.end(); j++) {
+				const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i;
+				auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i;
+				const auto complementary_var = find_complementary_pattern_var(left, right);
+
+				if (complementary_var && new_patterns.count(right)) {
+					new_patterns.erase(right);
+					right.erase(complementary_var.value());
+					new_patterns.insert(right);
+					optimized = true;
+				}
+			}
+		}
+		patterns = new_patterns;
+	} while(optimized);
+
+	// Remove redundant patterns
+	for (auto i = patterns.begin(); i != patterns.end(); ++i) {
+		for (auto j = std::next(i, 1); j != patterns.end(); ++j) {
+			const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i;
+			const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i;
+			bool redundant = true;
+
+			for (const auto& pt : left)
+				if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second)
+					redundant = false;
+			if (redundant)
+				new_patterns.erase(right);
+		}
+	}
+
+	patterns = std::move(new_patterns);
+}
+
+YOSYS_NAMESPACE_END
+
+#endif

kernel/rtlil.cc

@@ -31,6 +31,7 @@
 #include <charconv>
 #include <optional>
 #include <string_view>
+#include <sstream>
 
 YOSYS_NAMESPACE_BEGIN
 
@@ -185,7 +186,7 @@ struct IdStringCollector {
 		trace(selection_var.selected_modules);
 		trace(selection_var.selected_members);
 	}
-	void trace_named(const RTLIL::NamedObject named) {
+	void trace_named(const RTLIL::NamedObject &named) {
 		trace_keys(named.attributes);
 		trace(named.name);
 	}
@@ -1548,6 +1549,13 @@ void RTLIL::Design::pop_selection()
 		push_full_selection();
 }
 
+std::string RTLIL::Design::to_rtlil_str(bool only_selected) const
+{
+	std::ostringstream f;
+	RTLIL_BACKEND::dump_design(f, const_cast<RTLIL::Design*>(this), only_selected);
+	return f.str();
+}
+
 std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
 {
 	bool include_partials = partials == RTLIL::SELECT_ALL;
@@ -2982,6 +2990,8 @@ void RTLIL::Module::add(RTLIL::Binding *binding)
 void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 {
 	log_assert(refcount_wires_ == 0);
+	if (wires.empty())
+		return;
 
 	struct DeleteWireWorker
 	{
@@ -4288,6 +4298,13 @@ RTLIL::SigSpec RTLIL::Module::FutureFF(RTLIL::IdString name, const RTLIL::SigSpe
 	return sig;
 }
 
+std::string RTLIL::Module::to_rtlil_str() const
+{
+	std::ostringstream f;
+	RTLIL_BACKEND::dump_module(f, "", const_cast<RTLIL::Module*>(this), design, false);
+	return f.str();
+}
+
 RTLIL::Wire::Wire()
 {
 	static unsigned int hashidx_count = 123456789;
@@ -4315,6 +4332,13 @@ RTLIL::Wire::~Wire()
 #endif
 }
 
+std::string RTLIL::Wire::to_rtlil_str() const
+{
+	std::ostringstream f;
+	RTLIL_BACKEND::dump_wire(f, "", this);
+	return f.str();
+}
+
 #ifdef YOSYS_ENABLE_PYTHON
 static std::map<unsigned int, RTLIL::Wire*> all_wires;
 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void)
@@ -4337,6 +4361,13 @@ RTLIL::Memory::Memory()
 #endif
 }
 
+std::string RTLIL::Memory::to_rtlil_str() const
+{
+	std::ostringstream f;
+	RTLIL_BACKEND::dump_memory(f, "", this);
+	return f.str();
+}
+
 RTLIL::Process::Process() : module(nullptr)
 {
 	static unsigned int hashidx_count = 123456789;
@@ -4344,6 +4375,13 @@ RTLIL::Process::Process() : module(nullptr)
 	hashidx_ = hashidx_count;
 }
 
+std::string RTLIL::Process::to_rtlil_str() const
+{
+	std::ostringstream f;
+	RTLIL_BACKEND::dump_proc(f, "", this);
+	return f.str();
+}
+
 RTLIL::Cell::Cell() : module(nullptr)
 {
 	static unsigned int hashidx_count = 123456789;
@@ -4365,6 +4403,13 @@ RTLIL::Cell::~Cell()
 #endif
 }
 
+std::string RTLIL::Cell::to_rtlil_str() const
+{
+	std::ostringstream f;
+	RTLIL_BACKEND::dump_cell(f, "", this);
+	return f.str();
+}
+
 #ifdef YOSYS_ENABLE_PYTHON
 static std::map<unsigned int, RTLIL::Cell*> all_cells;
 std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)

kernel/rtlil.h

@@ -2031,7 +2031,10 @@ struct RTLIL::Design
 	// returns all selected unboxed whole modules, warning the user if any
 	// partially selected or boxed modules have been ignored
 	std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
+
 	static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
+
+	std::string to_rtlil_str(bool only_selected = true) const;
 };
 
 struct RTLIL::Module : public RTLIL::NamedObject
@@ -2395,6 +2398,7 @@ public:
 	RTLIL::SigSpec OriginalTag     (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
 	RTLIL::SigSpec FutureFF        (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
 
+	std::string to_rtlil_str() const;
 #ifdef YOSYS_ENABLE_PYTHON
 	static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
 #endif
@@ -2448,6 +2452,7 @@ public:
 		return zero_index + start_offset;
 	}
 
+	std::string to_rtlil_str() const;
 #ifdef YOSYS_ENABLE_PYTHON
 	static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
 #endif
@@ -2465,6 +2470,8 @@ struct RTLIL::Memory : public RTLIL::NamedObject
 	Memory();
 
 	int width, start_offset, size;
+
+	std::string to_rtlil_str() const;
 #ifdef YOSYS_ENABLE_PYTHON
 	~Memory();
 	static std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);
@@ -2523,6 +2530,8 @@ public:
 	template<typename T> void rewrite_sigspecs(T &functor);
 	template<typename T> void rewrite_sigspecs2(T &functor);
 
+	std::string to_rtlil_str() const;
+
 #ifdef YOSYS_ENABLE_PYTHON
 	static std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);
 #endif
@@ -2601,6 +2610,7 @@ public:
 	template<typename T> void rewrite_sigspecs(T &functor);
 	template<typename T> void rewrite_sigspecs2(T &functor);
 	RTLIL::Process *clone() const;
+	std::string to_rtlil_str() const;
 };
 
 

passes/cmds/Makefile.inc

@@ -37,6 +37,7 @@ OBJS += passes/cmds/chformal.o
 OBJS += passes/cmds/chtype.o
 OBJS += passes/cmds/blackbox.o
 OBJS += passes/cmds/ltp.o
+OBJS += passes/cmds/linux_perf.o
 ifeq ($(DISABLE_SPAWN),0)
 OBJS += passes/cmds/bugpoint.o
 endif

passes/cmds/design_equal.cc

@@ -30,6 +30,21 @@ class ModuleComparator
 public:
 	ModuleComparator(RTLIL::Module *mod_a, RTLIL::Module *mod_b) : mod_a(mod_a), mod_b(mod_b) {}
 
+	template <typename... Args>
+	[[noreturn]] void error(FmtString<TypeIdentity<Args>...> fmt, const Args &... args)
+	{
+		formatted_error(fmt.format(args...));
+	}
+	[[noreturn]]
+	void formatted_error(std::string err)
+	{
+		log("Module A: %s\n", log_id(mod_a->name));
+		log_module(mod_a, "  ");
+		log("Module B: %s\n", log_id(mod_b->name));
+		log_module(mod_b, "  ");
+		log_cmd_error("Designs are different: %s\n", err);
+	}
+
 	bool compare_sigbit(const RTLIL::SigBit &a, const RTLIL::SigBit &b)
 	{
 		if (a.wire == nullptr && b.wire == nullptr)
@@ -90,13 +105,13 @@ public:
 	{
 		for (const auto &it : mod_a->wires_) {
 			if (mod_b->wires_.count(it.first) == 0)
-				log_error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first));
+				error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first));
 			if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty())
-				log_error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
+				error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
 		}
 		for (const auto &it : mod_b->wires_)
 			if (mod_a->wires_.count(it.first) == 0)
-				log_error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first));
+				error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first));
 	}
 
 	std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b)
@@ -150,26 +165,26 @@ public:
 	{
 		for (const auto &it : mod_a->cells_) {
 			if (mod_b->cells_.count(it.first) == 0)
-				log_error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first));
+				error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first));
 			if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty())
-				log_error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
+				error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
 		}
 		for (const auto &it : mod_b->cells_)
 			if (mod_a->cells_.count(it.first) == 0)
-				log_error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first));
+				error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first));
 	}
 
 	void check_memories()
 	{
 		for (const auto &it : mod_a->memories) {
 			if (mod_b->memories.count(it.first) == 0)
-				log_error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first));
+				error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first));
 			if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty())
-				log_error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
+				error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
 		}
 		for (const auto &it : mod_b->memories)
 			if (mod_a->memories.count(it.first) == 0)
-				log_error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first));
+				error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first));
 	}
 
 	std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b)
@@ -270,13 +285,13 @@ public:
 	{
 		for (auto &it : mod_a->processes) {
 			if (mod_b->processes.count(it.first) == 0)
-				log_error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first));
+				error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first));
 			if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty())
-				log_error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str());
+				error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str());
 		}
 		for (auto &it : mod_b->processes)
 			if (mod_a->processes.count(it.first) == 0)
-				log_error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first));
+				error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first));
 	}
 
 	void check_connections()
@@ -284,13 +299,13 @@ public:
 		const auto &conns_a = mod_a->connections();
 		const auto &conns_b = mod_b->connections();
 		if (conns_a.size() != conns_b.size()) {
-			log_error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size());
+			error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size());
 		} else {
 			for (size_t i = 0; i < conns_a.size(); i++) {
 				if (!compare_sigspec(conns_a[i].first, conns_b[i].first))
-					log_error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
+					error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
 				if (!compare_sigspec(conns_a[i].second, conns_b[i].second))
-					log_error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
+					error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
 			}
 		}
 	}
@@ -298,9 +313,9 @@ public:
 	void check()
 	{
 		if (mod_a->name != mod_b->name)
-			log_error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name));
+			error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name));
 		if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty())
-			log_error("Module %s %s.\n", log_id(mod_a->name), mismatch);
+			error("Module %s %s.\n", log_id(mod_a->name), mismatch);
 		check_wires();
 		check_cells();
 		check_memories();

passes/cmds/linux_perf.cc

@@ -0,0 +1,102 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2014  Claire Xenia Wolf <claire@yosyshq.com>
+ *  Copyright (C) 2014  Johann Glaser <Johann.Glaser@gmx.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/log_help.h"
+
+#include <fcntl.h>
+#include <stdlib.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#ifdef __linux__
+#include <unistd.h>
+struct LinuxPerf : public Pass {
+	LinuxPerf() : Pass("linux_perf", "turn linux perf recording off or on") {
+		internal();
+	}
+	bool formatted_help() override
+	{
+		auto *help = PrettyHelp::get_current();
+		
+		auto content_root = help->get_root();
+
+		content_root->usage("linux_perf [on|off]");
+
+		content_root->paragraph(
+			"This pass turns Linux 'perf' profiling on or off, when it has been configured to use control FIFOs."
+			"YOSYS_PERF_CTL and YOSYS_PERF_ACK must point to Linux perf control FIFOs."
+		);
+		content_root->paragraph("Example shell command line:");
+		content_root->codeblock(
+			"mkfifo /tmp/perf.fifo /tmp/perf-ack.fifo\n"
+			"YOSYS_PERF_CTL=/tmp/perf.fifo YOSYS_PERF_ACK=/tmp/perf-ack.fifo \\\n"
+			"  perf record --latency --delay=-1 \\\n"
+			"  --control=fifo:/tmp/perf.fifo,/tmp/perf-ack.fifo --call-graph=dwarf ./yosys \\\n"
+			"  -dt -p \"read_rtlil design.rtlil; linux_perf on; opt_clean; linux_perf off\"\n"
+		);
+
+		return true;
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *) override
+	{
+		if (args.size() > 2)
+			cmd_error(args, 2, "Unexpected argument.");
+
+		std::string_view ctl_msg;
+		if (args.size() == 2) {
+			if (args[1] == "on")
+				ctl_msg = "enable\n";
+			else if (args[1] == "off")
+				ctl_msg = "disable\n";
+			else
+				cmd_error(args, 1, "Unexpected argument.");
+		}
+
+		const char *ctl_fifo = std::getenv("YOSYS_PERF_CTL");
+		if (!ctl_fifo)
+			log_error("YOSYS_PERF_CTL environment variable not set.");
+		const char *ack_fifo = std::getenv("YOSYS_PERF_ACK");
+		if (!ack_fifo)
+			log_error("YOSYS_PERF_ACK environment variable not set.");
+
+		int ctl_fd = open(ctl_fifo, O_WRONLY);
+		if (ctl_fd < 0)
+			log_error("Failed to open YOSYS_PERF_CTL.");
+		int ack_fd = open(ack_fifo, O_RDONLY);
+		if (ack_fd < 0)
+			log_error("Failed to open YOSYS_PERF_ACK.");
+		int result = write(ctl_fd, ctl_msg.data(), ctl_msg.size());
+		if (result != static_cast<int>(ctl_msg.size()))
+			log_error("Failed to write to YOSYS_PERF_CTL.");
+		char buffer[64];
+		result = read(ack_fd, buffer, sizeof(buffer));
+		close(ctl_fd);
+		close(ack_fd);
+		if (result <= 0)
+			log_error("Failed to read from YOSYS_PERF_ACK.");
+		if (strcmp(buffer, "ack\n") != 0)
+			log_error("YOSYS_PERF_ACK did not return 'ack'.");
+	}
+} LinuxPerf;
+#endif
+
+PRIVATE_NAMESPACE_END

passes/cmds/trace.cc

@@ -115,16 +115,45 @@ struct DebugPass : public Pass {
 		log("\n");
 		log("Execute the specified command with debug log messages enabled\n");
 		log("\n");
+		log("    debug -on\n");
+		log("    debug -off\n");
+		log("\n");
+		log("Enable or disable debug log messages globally\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		size_t argidx;
+		bool mode_on = false;
+		bool mode_off = false;
+
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// .. parse options ..
+			if (args[argidx] == "-on") {
+				mode_on = true;
+				continue;
+			}
+			if (args[argidx] == "-off") {
+				mode_off = true;
+				continue;
+			}
 			break;
 		}
 
+		if (mode_on && mode_off)
+			log_cmd_error("Cannot specify both -on and -off\n");
+
+		if (mode_on) {
+			log_force_debug++;
+			return;
+		}
+
+		if (mode_off) {
+			if (log_force_debug > 0)
+				log_force_debug--;
+			return;
+		}
+
 		log_force_debug++;
 
 		try {

passes/opt/Makefile.inc

@@ -23,6 +23,7 @@ OBJS += passes/opt/opt_lut_ins.o
 OBJS += passes/opt/opt_ffinv.o
 OBJS += passes/opt/pmux2shiftx.o
 OBJS += passes/opt/muxpack.o
+OBJS += passes/opt/opt_balance_tree.o
 
 OBJS += passes/opt/peepopt.o
 GENFILES += passes/opt/peepopt_pm.h

passes/opt/opt.cc

@@ -193,7 +193,6 @@ struct OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");

passes/opt/opt_balance_tree.cc

@@ -0,0 +1,379 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *                2019  Eddie Hung        <eddie@fpgeh.com>
+ *                2024  Akash Levy        <akash@silimate.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <deque>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+
+struct OptBalanceTreeWorker {
+	// Module and signal map
+	Module *module;
+	SigMap sigmap;
+
+	// Counts of each cell type that are getting balanced
+	dict<IdString, int> cell_count;
+
+	// Check if cell is of the right type and has matching input/output widths
+	// Only allow cells with "natural" output widths (no truncation) to prevent
+	// equivalence issues when rebalancing (see YosysHQ/yosys#5605)
+	bool is_right_type(Cell* cell, IdString cell_type) {
+		if (cell->type != cell_type)
+			return false;
+
+		int y_width = cell->getParam(ID::Y_WIDTH).as_int();
+		int a_width = cell->getParam(ID::A_WIDTH).as_int();
+		int b_width = cell->getParam(ID::B_WIDTH).as_int();
+
+		// Calculate the "natural" output width for this operation
+		int natural_width;
+		if (cell_type == ID($add)) {
+			// Addition produces max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
+			natural_width = std::max(a_width, b_width) + 1;
+		} else if (cell_type == ID($mul)) {
+			// Multiplication produces A_WIDTH + B_WIDTH
+			natural_width = a_width + b_width;
+		} else {
+			// Logic operations ($and/$or/$xor) produce max(A_WIDTH, B_WIDTH)
+			natural_width = std::max(a_width, b_width);
+		}
+
+		// Only allow cells where Y_WIDTH >= natural width (no truncation)
+		// This prevents rebalancing chains where truncation semantics matter
+		return y_width >= natural_width;
+	}
+
+	// Create a balanced binary tree from a vector of source signals
+	SigSpec create_balanced_tree(vector<SigSpec> &sources, IdString cell_type, Cell* cell) {
+		// Base case: if we have no sources, return an empty signal
+		if (sources.size() == 0)
+			return SigSpec();
+
+		// Base case: if we have only one source, return it
+		if (sources.size() == 1)
+			return sources[0];
+		
+		// Base case: if we have two sources, create a single cell
+		if (sources.size() == 2) {
+			// Create a new cell of the same type
+			Cell* new_cell = module->addCell(NEW_ID, cell_type);
+			
+			// Copy attributes from reference cell
+			new_cell->attributes = cell->attributes;
+			
+			// Create output wire
+			int out_width = cell->getParam(ID::Y_WIDTH).as_int();
+			if (cell_type == ID($add))
+				out_width = max(sources[0].size(), sources[1].size()) + 1;
+			else if (cell_type == ID($mul))
+				out_width = sources[0].size() + sources[1].size();
+			Wire* out_wire = module->addWire(NEW_ID, out_width);
+			
+			// Connect ports and fix up parameters
+			new_cell->setPort(ID::A, sources[0]);
+			new_cell->setPort(ID::B, sources[1]);
+			new_cell->setPort(ID::Y, out_wire);
+			new_cell->fixup_parameters();
+			new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
+			new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
+			
+			// Update count and return output wire
+			cell_count[cell_type]++;
+			return out_wire;
+		}
+		
+		// Recursive case: split sources into two groups and create subtrees
+		int mid = (sources.size() + 1) / 2;
+		vector<SigSpec> left_sources(sources.begin(), sources.begin() + mid);
+		vector<SigSpec> right_sources(sources.begin() + mid, sources.end());
+		
+		SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell);
+		SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
+		
+		// Create a cell to combine the two subtrees
+		Cell* new_cell = module->addCell(NEW_ID, cell_type);
+		
+		// Copy attributes from reference cell
+		new_cell->attributes = cell->attributes;
+		
+		// Create output wire
+		int out_width = cell->getParam(ID::Y_WIDTH).as_int();
+		if (cell_type == ID($add))
+			out_width = max(left_tree.size(), right_tree.size()) + 1;
+		else if (cell_type == ID($mul))
+			out_width = left_tree.size() + right_tree.size();
+		Wire* out_wire = module->addWire(NEW_ID, out_width);
+		
+		// Connect ports and fix up parameters
+		new_cell->setPort(ID::A, left_tree);
+		new_cell->setPort(ID::B, right_tree);
+		new_cell->setPort(ID::Y, out_wire);
+		new_cell->fixup_parameters();
+		new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
+		new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
+		
+		// Update count and return output wire
+		cell_count[cell_type]++;
+		return out_wire;
+	}
+
+	OptBalanceTreeWorker(Module *module, const vector<IdString> cell_types) : module(module), sigmap(module) {
+		// Do for each cell type
+		for (auto cell_type : cell_types) {
+			// Index all of the nets in the module
+			dict<SigSpec, Cell*> sig_to_driver;
+			dict<SigSpec, pool<Cell*>> sig_to_sink;
+			for (auto cell : module->selected_cells())
+			{
+				for (auto &conn : cell->connections())
+				{
+					if (cell->output(conn.first))
+						sig_to_driver[sigmap(conn.second)] = cell;
+
+					if (cell->input(conn.first))
+					{
+						SigSpec sig = sigmap(conn.second);
+						if (sig_to_sink.count(sig) == 0)
+							sig_to_sink[sig] = pool<Cell*>();
+						sig_to_sink[sig].insert(cell);
+					}
+				}
+			}
+
+			// Need to check if any wires connect to module ports
+			pool<SigSpec> input_port_sigs;
+			pool<SigSpec> output_port_sigs;
+			for (auto wire : module->selected_wires())
+				if (wire->port_input || wire->port_output) {
+					SigSpec sig = sigmap(wire);
+					for (auto bit : sig) {
+						if (wire->port_input)
+							input_port_sigs.insert(bit);
+						if (wire->port_output)
+							output_port_sigs.insert(bit);
+					}
+				}
+
+			// Actual logic starts here
+			pool<Cell*> consumed_cells;
+			for (auto cell : module->selected_cells())
+			{
+				// If consumed or not the correct type, skip
+				if (consumed_cells.count(cell) || !is_right_type(cell, cell_type))
+					continue;
+
+				// BFS, following all chains until they hit a cell of a different type
+				// Pick the longest one
+				auto y = sigmap(cell->getPort(ID::Y));
+				pool<Cell*> sinks;
+				pool<Cell*> current_loads = sig_to_sink[y];
+				pool<Cell*> next_loads;
+				while (!current_loads.empty())
+				{
+					// Find each sink and see what they are
+					for (auto x : current_loads)
+					{
+						// If not the correct type, don't follow any further
+						// (but add the originating cell to the list of sinks)
+						if (!is_right_type(x, cell_type))
+						{
+							sinks.insert(cell);
+							continue;
+						}
+
+						auto xy = sigmap(x->getPort(ID::Y));
+
+						// If this signal drives a port, add it to the sinks
+						// (even though it may not be the end of a chain)
+						for (auto bit : xy) {
+							if (output_port_sigs.count(bit) && !consumed_cells.count(x)) {
+								sinks.insert(x);
+								break;
+							}
+						}
+
+						// Search signal's fanout
+						auto& next = sig_to_sink[xy];
+						for (auto z : next)
+							next_loads.insert(z);
+					}
+
+					// If we couldn't find any downstream loads, stop.
+					// Create a reduction for each of the max-length chains we found
+					if (next_loads.empty())
+					{
+						for (auto s : current_loads)
+						{
+							// Not one of our gates? Don't follow any further
+							if (!is_right_type(s, cell_type))
+								continue;
+
+							sinks.insert(s);
+						}
+						break;
+					}
+
+					// Otherwise, continue down the chain
+					current_loads = next_loads;
+					next_loads.clear();
+				}
+
+				// We have our list of sinks, now go tree balance the chains
+				for (auto head_cell : sinks)
+				{
+					// Avoid duplication if we already were covered
+					if (consumed_cells.count(head_cell))
+						continue;
+
+					// Get sources of the chain
+					dict<SigSpec, int> sources;
+					dict<SigSpec, bool> signeds;
+					int inner_cells = 0;
+					std::deque<Cell*> bfs_queue = {head_cell};
+					while (bfs_queue.size())
+					{
+						Cell* x = bfs_queue.front();
+						bfs_queue.pop_front();
+
+						for (IdString port: {ID::A, ID::B}) {
+							auto sig = sigmap(x->getPort(port));
+							Cell* drv = sig_to_driver[sig];
+							bool drv_ok = drv && is_right_type(drv, cell_type);
+							for (auto bit : sig) {
+								if (input_port_sigs.count(bit) && !consumed_cells.count(drv)) {
+									drv_ok = false;
+									break;
+								}
+							}
+							if (drv_ok) {
+								inner_cells++;
+								bfs_queue.push_back(drv);
+							} else {
+								sources[sig]++;
+								signeds[sig] = x->getParam(port == ID::A ? ID::A_SIGNED : ID::B_SIGNED).as_bool();
+							}
+						}
+					}
+
+					if (inner_cells)
+					{
+						// Create a tree
+						log_debug("  Creating tree for %s with %d sources and %d inner cells...\n", log_id(head_cell), GetSize(sources), inner_cells);
+						
+						// Build a vector of all source signals
+						vector<SigSpec> source_signals;
+						vector<bool> signed_flags;
+						for (auto &source : sources) {
+							for (int i = 0; i < source.second; i++) {
+								source_signals.push_back(source.first);
+								signed_flags.push_back(signeds[source.first]);
+							}
+						}
+
+						// If not all signed flags are the same, do not balance
+						if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) {
+							continue;
+						}
+						
+						// Create the balanced tree
+						SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
+						
+						// Connect the tree output to the head cell's output
+						SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
+						int connect_width = std::min(head_output.size(), tree_output.size());
+						module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width));
+						if (head_output.size() > tree_output.size()) {
+							SigBit sext_bit = head_cell->getParam(ID::A_SIGNED).as_bool() ? head_output[connect_width - 1] : State::S0;
+							module->connect(head_output.extract(connect_width, head_output.size() - connect_width), SigSpec(sext_bit, head_output.size() - connect_width));
+						}
+
+						// Mark consumed cell for removal
+						consumed_cells.insert(head_cell);
+					}
+				}
+			}
+			
+			// Remove all consumed cells, which now have been replaced by trees
+			for (auto cell : consumed_cells)
+				module->remove(cell);
+		}
+	}
+};
+
+struct OptBalanceTreePass : public Pass {
+	OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$add/$mul cascades to trees") { }
+	void help() override {
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    opt_balance_tree [options] [selection]\n");
+		log("\n");
+		log("This pass converts cascaded chains of $and/$or/$xor/$add/$mul cells into\n");
+		log("trees of cells to improve timing.\n");
+		log("\n");
+		log("    -arith\n");
+		log("        only convert arithmetic cells.\n");
+		log("\n");
+		log("    -logic\n");
+		log("        only convert logic cells.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
+		log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n");
+		log_experimental("open_balance_tree");
+
+		// Handle arguments
+		size_t argidx;
+		vector<IdString> cell_types = {ID($and), ID($or), ID($xor), ID($add), ID($mul)};
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-arith") {
+				cell_types = {ID($add), ID($mul)};
+				continue;
+			}
+			if (args[argidx] == "-logic") {
+				cell_types = {ID($and), ID($or), ID($xor)};
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		// Count of all cells that were packed
+		dict<IdString, int> cell_count;
+		for (auto module : design->selected_modules()) {
+			OptBalanceTreeWorker worker(module, cell_types);
+			for (auto cell : worker.cell_count) {
+				cell_count[cell.first] += cell.second;
+			}
+		}
+
+		// Log stats
+		for (auto cell_type : cell_types)
+			log("Converted %d %s cells into trees.\n", cell_count[cell_type], log_id(cell_type));
+
+		// Clean up
+		Yosys::run_pass("clean -purge");
+	}
+} OptBalanceTreePass;
+
+PRIVATE_NAMESPACE_END

passes/opt/opt_clean.cc

@@ -271,6 +271,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs, SigPoo
 			return conns.check_any(s2);
 	}
 
+	if (w1 == w2)
+		return s2.offset < s1.offset;
+
 	if (w1->port_output != w2->port_output)
 		return w2->port_output;
 
@@ -343,7 +346,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		RTLIL::Wire *wire = it.second;
 		for (int i = 0; i < wire->width; i++) {
 			RTLIL::SigBit s1 = RTLIL::SigBit(wire, i), s2 = assign_map(s1);
-			if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
+			if (compare_signals(s2, s1, register_signals, connected_signals, direct_wires))
 				assign_map.add(s1);
 		}
 	}
@@ -467,8 +470,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 					wire->attributes.erase(ID::init);
 				else
 					wire->attributes.at(ID::init) = initval;
-				used_signals.add(new_conn.first);
-				used_signals.add(new_conn.second);
 				module->connect(new_conn);
 			}
 
@@ -715,7 +716,6 @@ struct OptCleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		keep_cache.reset();
@@ -780,7 +780,6 @@ struct CleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		keep_cache.reset();

passes/opt/opt_expr.cc

@@ -1667,7 +1667,11 @@ skip_identity:
 			int bit_idx;
 			const auto onehot = sig_a.is_onehot(&bit_idx);
 
-			if (onehot) {
+			// Power of two
+			// A is unsigned or positive
+			if (onehot && (!cell->parameters[ID::A_SIGNED].as_bool() || bit_idx < sig_a.size() - 1)) {
+				cell->parameters[ID::A_SIGNED] = 0;
+				// 2^B = 1<<B
 				if (bit_idx == 1) {
 					log_debug("Replacing pow cell `%s' in module `%s' with left-shift\n",
 							cell->name.c_str(), module->name.c_str());
@@ -1679,7 +1683,6 @@ skip_identity:
 					log_debug("Replacing pow cell `%s' in module `%s' with multiply and left-shift\n",
 							cell->name.c_str(), module->name.c_str());
 					cell->type = ID($mul);
-					cell->parameters[ID::A_SIGNED] = 0;
 					cell->setPort(ID::A, Const(bit_idx, cell->parameters[ID::A_WIDTH].as_int()));
 
 					SigSpec y_wire = module->addWire(NEW_ID, y_size);

passes/sat/sim.cc

@@ -549,31 +549,27 @@ struct SimInstance
 			if (shared->debug)
 				log("[%s] eval %s (%s)\n", hiername(), log_id(cell), log_id(cell->type));
 
-			// Simple (A -> Y) and (A,B -> Y) cells
-			if (has_a && !has_c && !has_d && !has_s && has_y) {
-				set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b)));
-				return;
-			}
+			bool err = false;
+			RTLIL::Const eval_state;
+			if (has_a && !has_c && !has_d && !has_s && has_y)
+				// Simple (A -> Y) and (A,B -> Y) cells
+				eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), &err);
+			else if (has_a && has_b && has_c && !has_d && !has_s && has_y)
+				// (A,B,C -> Y) cells
+				eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c), &err);
+			else if (has_a && !has_b && !has_c && !has_d && has_s && has_y)
+				// (A,S -> Y) cells
+				eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_s), &err);
+			else if (has_a && has_b && !has_c && !has_d && has_s && has_y)
+				// (A,B,S -> Y) cells
+				eval_state = CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s), &err);
+			else
+				err = true;
 
-			// (A,B,C -> Y) cells
-			if (has_a && has_b && has_c && !has_d && !has_s && has_y) {
-				set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_c)));
-				return;
-			}
-
-			// (A,S -> Y) cells
-			if (has_a && !has_b && !has_c && !has_d && has_s && has_y) {
-				set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_s)));
-				return;
-			}
-
-			// (A,B,S -> Y) cells
-			if (has_a && has_b && !has_c && !has_d && has_s && has_y) {
-				set_state(sig_y, CellTypes::eval(cell, get_state(sig_a), get_state(sig_b), get_state(sig_s)));
-				return;
-			}
-
-			log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
+			if (err)
+				log_warning("Unsupported evaluable cell type: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
+			else
+				set_state(sig_y, eval_state);
 			return;
 		}
 

passes/techmap/abc.cc

@@ -143,6 +143,14 @@ struct AbcConfig
 	bool markgroups = false;
 	pool<std::string> enabled_gates;
 	bool cmos_cost = false;
+
+	bool is_yosys_abc() const {
+#ifdef ABCEXTERNAL
+		return false;
+#else
+		return exe_file == yosys_abc_executable;
+#endif
+	}
 };
 
 struct AbcSigVal {
@@ -155,7 +163,12 @@ struct AbcSigVal {
 	}
 };
 
-#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN)
+// REUSE_YOSYS_ABC_PROCESSES only works when ABC is built with ENABLE_READLINE.
+#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN) && defined(YOSYS_ENABLE_READLINE)
+#define REUSE_YOSYS_ABC_PROCESSES
+#endif
+
+#ifdef REUSE_YOSYS_ABC_PROCESSES
 struct AbcProcess
 {
 	pid_t pid;
@@ -188,10 +201,10 @@ struct AbcProcess
 		int status;
 		int ret = waitpid(pid, &status, 0);
 		if (ret != pid) {
-			log_error("waitpid(%d) failed", pid);
+			log_error("waitpid(%d) failed\n", pid);
 		}
 		if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
-			log_error("ABC failed with status %X", status);
+			log_error("ABC failed with status %X\n", status);
 		}
 		if (from_child_pipe >= 0)
 			close(from_child_pipe);
@@ -203,12 +216,12 @@ std::optional<AbcProcess> spawn_abc(const char* abc_exe, DeferredLogs &logs) {
 	// fork()s.
 	int to_child_pipe[2];
 	if (pipe2(to_child_pipe, O_CLOEXEC) != 0) {
-		logs.log_error("pipe failed");
+		logs.log_error("pipe failed\n");
 		return std::nullopt;
 	}
 	int from_child_pipe[2];
 	if (pipe2(from_child_pipe, O_CLOEXEC) != 0) {
-		logs.log_error("pipe failed");
+		logs.log_error("pipe failed\n");
 		return std::nullopt;
 	}
 
@@ -221,39 +234,39 @@ std::optional<AbcProcess> spawn_abc(const char* abc_exe, DeferredLogs &logs) {
 
 	posix_spawn_file_actions_t file_actions;
 	if (posix_spawn_file_actions_init(&file_actions) != 0) {
-		logs.log_error("posix_spawn_file_actions_init failed");
+		logs.log_error("posix_spawn_file_actions_init failed\n");
 		return std::nullopt;
 	}
 
 	if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[1]) != 0) {
-		logs.log_error("posix_spawn_file_actions_addclose failed");
+		logs.log_error("posix_spawn_file_actions_addclose failed\n");
 		return std::nullopt;
 	}
 	if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[0]) != 0) {
-		logs.log_error("posix_spawn_file_actions_addclose failed");
+		logs.log_error("posix_spawn_file_actions_addclose failed\n");
 		return std::nullopt;
 	}
 	if (posix_spawn_file_actions_adddup2(&file_actions, to_child_pipe[0], STDIN_FILENO) != 0) {
-		logs.log_error("posix_spawn_file_actions_adddup2 failed");
+		logs.log_error("posix_spawn_file_actions_adddup2 failed\n");
 		return std::nullopt;
 	}
 	if (posix_spawn_file_actions_adddup2(&file_actions, from_child_pipe[1], STDOUT_FILENO) != 0) {
-		logs.log_error("posix_spawn_file_actions_adddup2 failed");
+		logs.log_error("posix_spawn_file_actions_adddup2 failed\n");
 		return std::nullopt;
 	}
 	if (posix_spawn_file_actions_addclose(&file_actions, to_child_pipe[0]) != 0) {
-		logs.log_error("posix_spawn_file_actions_addclose failed");
+		logs.log_error("posix_spawn_file_actions_addclose failed\n");
 		return std::nullopt;
 	}
 	if (posix_spawn_file_actions_addclose(&file_actions, from_child_pipe[1]) != 0) {
-		logs.log_error("posix_spawn_file_actions_addclose failed");
+		logs.log_error("posix_spawn_file_actions_addclose failed\n");
 		return std::nullopt;
 	}
 
 	char arg1[] = "-s";
 	char* argv[] = { strdup(abc_exe), arg1, nullptr };
 	if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) {
-		logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerror(errno));
+		logs.log_error("posix_spawnp %s failed (errno=%s)\n", abc_exe, strerror(errno));
 		return std::nullopt;
 	}
 	free(argv[0]);
@@ -1063,8 +1076,9 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 		abc_script += stringf("; dress \"%s/input.blif\"", run_abc.tempdir_name);
 	abc_script += stringf("; write_blif %s/output.blif", run_abc.tempdir_name);
 	abc_script = add_echos_to_abc_cmd(abc_script);
-#if defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN)
-	abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n";
+#if defined(REUSE_YOSYS_ABC_PROCESSES)
+	if (config.is_yosys_abc())
+		abc_script += "; echo; echo \"YOSYS_ABC_DONE\"\n";
 #endif
 
 	for (size_t i = 0; i+1 < abc_script.size(); i++)
@@ -1127,40 +1141,84 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 	handle_loops(assign_map, module);
 }
 
+#if defined(REUSE_YOSYS_ABC_PROCESSES)
+static bool is_abc_prompt(const std::string &line, std::string &rest) {
+	size_t pos = 0;
+	while (true) {
+		// The prompt may not start at the start of the line, because
+		// ABC can output progress and maybe other data that isn't
+		// newline-terminated.
+		size_t start = line.find("abc ", pos);
+		if (start == std::string::npos)
+			return false;
+		pos = start + 4;
+
+		size_t digits = 0;
+		while (pos + digits < line.size() && line[pos + digits] >= '0' && line[pos + digits] <= '9')
+			++digits;
+		if (digits < 2)
+			return false;
+		if (line.substr(pos + digits, 2) == "> ") {
+			rest = line.substr(pos + digits + 2);
+			return true;
+		}
+	}
+}
+
 bool read_until_abc_done(abc_output_filter &filt, int fd, DeferredLogs &logs) {
 	std::string line;
 	char buf[1024];
+	bool seen_source_cmd = false;
+	bool seen_yosys_abc_done = false;
 	while (true) {
 		int ret = read(fd, buf, sizeof(buf) - 1);
 		if (ret < 0) {
-			logs.log_error("Failed to read from ABC, errno=%d", errno);
+			logs.log_error("Failed to read from ABC, errno=%d\n", errno);
 			return false;
 		}
 		if (ret == 0) {
-			logs.log_error("ABC exited prematurely");
+			logs.log_error("ABC exited prematurely\n");
 			return false;
 		}
 		char *start = buf;
 		char *end = buf + ret;
 		while (start < end) {
 			char *p = static_cast<char*>(memchr(start, '\n', end - start));
-			if (p == nullptr) {
-				break;
+			char *upto = p == nullptr ? end : p + 1;
+			line.append(start, upto - start);
+			start = upto;
+
+			std::string rest;
+			bool is_prompt = is_abc_prompt(line, rest);
+			if (is_prompt && seen_source_cmd) {
+				// This is the first prompt after we sourced the script.
+				// We are done here.
+				// We won't have seen a newline yet since ABC is waiting at the prompt.
+				if (!seen_yosys_abc_done)
+					logs.log_error("ABC script did not complete successfully\n");
+				return seen_yosys_abc_done;
 			}
-			line.append(start, p + 1 - start);
-			if (line.substr(0, 14) == "YOSYS_ABC_DONE") {
-				// Ignore any leftover output, there should only be a prompt perhaps
-				return true;
+			if (line.empty() || line[line.size() - 1] != '\n') {
+				// No newline yet, wait for more text
+				continue;
 			}
 			filt.next_line(line);
+			if (is_prompt && rest.substr(0, 7) == "source ")
+				seen_source_cmd = true;
+			if (line.substr(0, 14) == "YOSYS_ABC_DONE")
+				seen_yosys_abc_done = true;
 			line.clear();
-			start = p + 1;
 		}
 		line.append(start, end - start);
 	}
 }
+#endif
 
+#if defined(REUSE_YOSYS_ABC_PROCESSES)
 void RunAbcState::run(ConcurrentStack<AbcProcess> &process_pool)
+#else
+void RunAbcState::run(ConcurrentStack<AbcProcess> &)
+#endif
 {
 	std::string buffer = stringf("%s/input.blif", tempdir_name);
 	FILE *f = fopen(buffer.c_str(), "wt");
@@ -1285,9 +1343,13 @@ void RunAbcState::run(ConcurrentStack<AbcProcess> &process_pool)
 
 	logs.log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
 			count_gates, GetSize(signal_list), count_input, count_output);
-	if (count_output > 0)
-	{
-		std::string tmp_script_name = stringf("%s/abc.script", tempdir_name);
+	if (count_output == 0) {
+		log("Don't call ABC as there is nothing to map.\n");
+		return;
+	}
+	int ret;
+	std::string tmp_script_name = stringf("%s/abc.script", tempdir_name);
+	do {
 		logs.log("Running ABC script: %s\n", replace_tempdir(tmp_script_name, tempdir_name, config.show_tempdir));
 
 		errno = 0;
@@ -1318,7 +1380,7 @@ void RunAbcState::run(ConcurrentStack<AbcProcess> &process_pool)
 		abc_argv[2] = strdup("-f");
 		abc_argv[3] = strdup(tmp_script_name.c_str());
 		abc_argv[4] = 0;
-		int ret = abc::Abc_RealMain(4, abc_argv);
+		ret = abc::Abc_RealMain(4, abc_argv);
 		free(abc_argv[0]);
 		free(abc_argv[1]);
 		free(abc_argv[2]);
@@ -1333,39 +1395,42 @@ void RunAbcState::run(ConcurrentStack<AbcProcess> &process_pool)
 		for (std::string line; std::getline(temp_stdouterr_r, line); )
 			filt.next_line(line + "\n");
 		temp_stdouterr_r.close();
-#elif defined(__linux__) && !defined(YOSYS_DISABLE_SPAWN)
-		AbcProcess process;
-		if (std::optional<AbcProcess> process_opt = process_pool.try_pop_back()) {
-			process = std::move(process_opt.value());
-		} else if (std::optional<AbcProcess> process_opt = spawn_abc(config.exe_file.c_str(), logs)) {
-			process = std::move(process_opt.value());
-		} else {
-			return;
-		}
-		std::string cmd = stringf(
-				"empty\n"
-				"source %s\n", tmp_script_name);
-		int ret = write(process.to_child_pipe, cmd.c_str(), cmd.size());
-		if (ret != static_cast<int>(cmd.size())) {
-			logs.log_error("write failed");
-			return;
-		}
-		ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1;
-		if (ret == 0) {
-			process_pool.push_back(std::move(process));
-		}
+		break;
 #else
-		std::string cmd = stringf("\"%s\" -s -f %s/abc.script 2>&1", config.exe_file.c_str(), tempdir_name.c_str());
-		int ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
-#endif
-		if (ret != 0) {
-			logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno);
-			return;
+#if defined(REUSE_YOSYS_ABC_PROCESSES)
+		if (config.is_yosys_abc()) {
+			AbcProcess process;
+			if (std::optional<AbcProcess> process_opt = process_pool.try_pop_back()) {
+				process = std::move(process_opt.value());
+			} else if (std::optional<AbcProcess> process_opt = spawn_abc(config.exe_file.c_str(), logs)) {
+				process = std::move(process_opt.value());
+			} else {
+				return;
+			}
+			std::string cmd = stringf(
+					"empty\n"
+					"source %s\n", tmp_script_name);
+			ret = write(process.to_child_pipe, cmd.c_str(), cmd.size());
+			if (ret != static_cast<int>(cmd.size())) {
+				logs.log_error("write failed");
+				return;
+			}
+			ret = read_until_abc_done(filt, process.from_child_pipe, logs) ? 0 : 1;
+			if (ret == 0) {
+				process_pool.push_back(std::move(process));
+			}
+			break;
 		}
-		did_run = true;
+#endif
+		std::string cmd = stringf("\"%s\" -s -f %s 2>&1", config.exe_file, tmp_script_name);
+		ret = run_command(cmd, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
+#endif
+	} while (false);
+	if (ret != 0) {
+		logs.log_error("ABC: execution of script \"%s\" failed: return code %d (errno=%d).\n", tmp_script_name, ret, errno);
 		return;
 	}
-	log("Don't call ABC as there is nothing to map.\n");
+	did_run = true;
 }
 
 void emit_global_input_files(const AbcConfig &config)

passes/techmap/dffunmap.cc

@@ -78,7 +78,6 @@ struct DffunmapPass : public Pass {
 					continue;
 
 				FfData ff(&initvals, cell);
-				IdString name = cell->name;
 
 				if (!ff.has_clk)
 					continue;

passes/techmap/lut2mux.cc

@@ -23,7 +23,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-int lut2mux(Cell *cell)
+int lut2mux(Cell *cell, bool word_mode)
 {
 	SigSpec sig_a = cell->getPort(ID::A);
 	SigSpec sig_y = cell->getPort(ID::Y);
@@ -32,7 +32,10 @@ int lut2mux(Cell *cell)
 
 	if (GetSize(sig_a) == 1)
 	{
-		cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
+		if (!word_mode)
+			cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); 
+		else
+		    cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
 	}
 	else
 	{
@@ -44,10 +47,13 @@ int lut2mux(Cell *cell)
 		Const lut1 = lut.extract(0, GetSize(lut)/2);
 		Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);
 
-		count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1));
-		count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2));
+		count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); 
+		count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode);
 
-		cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
+		if (!word_mode)
+			cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); 
+		else
+			cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y);
 	}
 
 	cell->module->remove(cell);
@@ -55,26 +61,33 @@ int lut2mux(Cell *cell)
 }
 
 struct Lut2muxPass : public Pass {
-	Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
+	Lut2muxPass() : Pass("lut2mux", "convert $lut to $mux/$_MUX_") { }
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    lut2mux [options] [selection]\n");
 		log("\n");
-		log("This pass converts $lut cells to $_MUX_ gates.\n");
+		log("This pass converts $lut cells to $mux/$_MUX_ gates.\n");
+		log("\n");
+		log("    -word\n");
+		log("        Convert $lut cells with a single input to word-level $mux gates.\n");
+		log("   	   The default is to convert them to bit-level $_MUX_ gates.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
+		log_header(design, "Executing LUT2MUX pass (convert $lut to $mux/$_MUX_).\n");
+			log("ARGS:"); for (auto &a: args) log(" [%s]", a.c_str()); log("\n");
 
 		size_t argidx;
+		bool word_mode = false;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-v") {
-			// 	continue;
-			// }
+			if (args[argidx] == "-word") {
+				word_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -83,7 +96,7 @@ struct Lut2muxPass : public Pass {
 		for (auto cell : module->selected_cells()) {
 			if (cell->type == ID($lut)) {
 				IdString cell_name = cell->name;
-				int count = lut2mux(cell);
+				int count = lut2mux(cell, word_mode);
 				log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);
 			}
 		}

passes/techmap/techmap.cc

@@ -333,9 +333,6 @@ struct TechmapWorker
 
 			RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
 			design->select(module, c);
-
-			if (c->type.begins_with("\\$"))
-				c->type = c->type.substr(1);
 			
 			if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) {
 				c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
@@ -436,13 +433,9 @@ struct TechmapWorker
 			if (handled_cells.count(cell) > 0)
 				continue;
 
-			std::string cell_type = cell->type.str();
-			if (in_recursion && cell->type.begins_with("\\$"))
-				cell_type = cell_type.substr(1);
-
-			if (celltypeMap.count(cell_type) == 0) {
-				if (assert_mode && cell_type.back() != '_')
-					log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
+			if (celltypeMap.count(cell->type) == 0) {
+				if (assert_mode && !cell->type.ends_with("_"))
+					log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
 				continue;
 			}
 
@@ -454,7 +447,7 @@ struct TechmapWorker
 				if (GetSize(sig) == 0)
 					continue;
 
-				for (auto &tpl_name : celltypeMap.at(cell_type)) {
+				for (auto &tpl_name : celltypeMap.at(cell->type)) {
 					RTLIL::Module *tpl = map->module(tpl_name);
 					RTLIL::Wire *port = tpl->wire(conn.first);
 					if (port && port->port_input)
@@ -481,12 +474,7 @@ struct TechmapWorker
 			log_assert(cell == module->cell(cell->name));
 			bool mapped_cell = false;
 
-			std::string cell_type = cell->type.str();
-
-			if (in_recursion && cell->type.begins_with("\\$"))
-				cell_type = cell_type.substr(1);
-
-			for (auto &tpl_name : celltypeMap.at(cell_type))
+			for (auto &tpl_name : celltypeMap.at(cell->type))
 			{
 				IdString derived_name = tpl_name;
 				RTLIL::Module *tpl = map->module(tpl_name);
@@ -508,8 +496,6 @@ struct TechmapWorker
 
 				if (!extmapper_name.empty())
 				{
-					cell->type = cell_type;
-
 					if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
 					{
 						std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type));
@@ -935,11 +921,6 @@ struct TechmapWorker
 						RTLIL::Module *m = design->addModule(m_name);
 						tpl->cloneInto(m);
 
-						for (auto cell : m->cells()) {
-							if (cell->type.begins_with("\\$"))
-								cell->type = cell->type.substr(1);
-						}
-
 						module_queue.insert(m);
 					}
 
@@ -1168,7 +1149,7 @@ struct TechmapPass : public Pass {
 
 		std::vector<std::string> map_files;
 		std::vector<RTLIL::IdString> dont_map;
-		std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
+		std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells";
 		int max_iter = -1;
 
 		size_t argidx;

pyosys/generator.py

@@ -701,6 +701,16 @@ class PyosysWrapperGenerator(object):
 
         self.process_class_members(metadata, metadata, cls, basename)
 
+        if basename == "Design":
+            print(
+                '\t\t\t.def("run_pass", [](Design &s, std::vector<std::string> cmd) { Pass::call(&s, cmd); })',
+                file=self.f,
+            )
+            print(
+                '\t\t\t.def("run_pass", [](Design &s, std::string cmd) { Pass::call(&s, cmd); })',
+                file=self.f,
+            )
+
         if expr := metadata.string_expr:
             print(
                 f'\t\t.def("__str__", [](const {basename} &s) {{ return {expr}; }})',

techlibs/common/prep.cc

@@ -211,6 +211,7 @@ struct PrepPass : public ScriptPass
 				run("memory_collect");
 			}
 			run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
+			run("sort");
 		}
 
 		if (check_label("check"))

techlibs/fix_mod.py

@@ -0,0 +1,47 @@
+import sys
+import subprocess
+import re
+import os
+
+def main():
+    script = sys.argv.pop(0)
+    try:
+        verilog, yosys = sys.argv
+    except ValueError:
+        print(f"Expected to be called as 'python3 {script} <cells_file> <yosys>'.")
+        exit(1)
+
+    proc = subprocess.run([yosys, '-p', f'read_verilog -lib {verilog}; write_verilog -blackboxes -'], stdout=subprocess.PIPE)
+    modules = {}
+    in_mod = False
+    mod = ""
+    decl = ""
+    for line in proc.stdout.decode('utf-8').splitlines(keepends=True):
+        m = re.match(r'(module (\S+)\(.+)', line, re.S)
+        if m:
+            decl, mod = m.groups()
+            in_mod = True
+        elif in_mod:
+            decl += line
+            
+        if in_mod and decl.rstrip()[-1] == ';':
+                in_mod = False
+                modules[mod] = decl
+
+    src = f'{verilog}.tmp'
+    os.rename(verilog, src)
+    dest = verilog
+
+    with open(dest, 'w') as f_out:
+        with open(src, 'r') as f_in:
+            for line in f_in:
+                m = re.match(r'module (\S+) \(\.\.\.\)', line)
+                if m:
+                    line = modules[m.group(1)]
+                print(line, end='', file=f_out)
+
+    if src.endswith('.tmp'):
+        os.remove(src)
+
+if __name__ == "__main__":
+    main()

techlibs/gowin/cells_xtra_gw1n.v

@@ -1,41 +1,41 @@
 // Created by cells_xtra.py
 
 
-module LUT5 (...);
+module LUT5(I0, I1, I2, I3, I4, F);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
 output F;
 endmodule
 
 
-module LUT6 (...);
+module LUT6(I0, I1, I2, I3, I4, I5, F);
 parameter INIT = 64'h0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5;
 output F;
 endmodule
 
 
-module LUT7 (...);
+module LUT7(I0, I1, I2, I3, I4, I5, I6, F);
 parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5, I6;
 output F;
 endmodule
 
 
-module LUT8 (...);
+module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F);
 parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5, I6, I7;
 output F;
 endmodule
 
 
-module INV (...);
+module INV(I, O);
 input  I;
 output O;
 endmodule
 
 
-module IODELAY (...);
+module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
 parameter C_STATIC_DLY = 0; 
 input DI;
 input  SDTAP;
@@ -46,7 +46,7 @@ output DO;
 endmodule
 
 
-module IEM (...);
+module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
 parameter WINSIZE = "SMALL"; 
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
@@ -55,14 +55,14 @@ output LAG, LEAD;
 endmodule
 
 
-module ROM16 (...);
+module ROM16(AD, DO);
 parameter INIT_0 = 16'h0000;
 input [3:0] AD;
 output DO;
 endmodule
 
 
-module ROM (...);
+module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
 parameter BLK_SEL = 3'b000;
@@ -141,7 +141,7 @@ output [31:0] DO;
 endmodule
 
 
-module ROMX9 (...);
+module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 36; 
 parameter BLK_SEL = 3'b000;
@@ -220,7 +220,7 @@ output [35:0] DO;
 endmodule
 
 
-module pROM (...);
+module pROM(CLK, CE, OCE, RESET, AD, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
 parameter RESET_MODE = "SYNC"; 
@@ -296,7 +296,7 @@ output [31:0] DO;
 endmodule
 
 
-module pROMX9 (...);
+module pROMX9(CLK, CE, OCE, RESET, AD, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 36; 
 parameter RESET_MODE = "SYNC"; 
@@ -372,7 +372,7 @@ output [35:0] DO;
 endmodule
 
 
-module SDPB (...);
+module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 32; 
 parameter BIT_WIDTH_1 = 32; 
@@ -453,7 +453,7 @@ output [31:0] DO;
 endmodule
 
 
-module SDPX9B (...);
+module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 36; 
 parameter BIT_WIDTH_1 = 36; 
@@ -534,7 +534,7 @@ output [35:0] DO;
 endmodule
 
 
-module DPB (...);
+module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
 parameter READ_MODE0 = 1'b0; 
 parameter READ_MODE1 = 1'b0; 
 parameter WRITE_MODE0 = 2'b00; 
@@ -619,7 +619,7 @@ output [15:0] DOA, DOB;
 endmodule
 
 
-module DPX9B (...);
+module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
 parameter READ_MODE0 = 1'b0; 
 parameter READ_MODE1 = 1'b0; 
 parameter WRITE_MODE0 = 2'b00; 
@@ -704,7 +704,7 @@ output [17:0] DOA, DOB;
 endmodule
 
 
-module PADD18 (...);
+module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
 input  [17:0] A;
 input  [17:0] B;
 input  ASEL;
@@ -720,7 +720,7 @@ parameter BSEL_MODE = 1'b1;
 parameter SOREG = 1'b0;
 endmodule
 
-module PADD9 (...);
+module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
 input  [8:0] A;
 input  [8:0] B;
 input  ASEL;
@@ -736,7 +736,7 @@ parameter BSEL_MODE = 1'b1;
 parameter SOREG = 1'b0;
 endmodule
 
-module MULT9X9 (...);
+module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
 input  [8:0] A,SIA;
 input  [8:0] B,SIB;
 input  ASIGN,BSIGN;
@@ -756,7 +756,7 @@ parameter SOA_REG = 1'b0;
 parameter MULT_RESET_MODE = "SYNC"; 
 endmodule
 
-module MULT18X18 (...);
+module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
 input  [17:0] A,SIA;
 input  [17:0] B,SIB;
 input  ASIGN,BSIGN;
@@ -776,7 +776,7 @@ parameter SOA_REG = 1'b0;
 parameter MULT_RESET_MODE = "SYNC"; 
 endmodule
 
-module MULT36X36 (...);
+module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
 input  [35:0] A;
 input  [35:0] B;
 input  ASIGN,BSIGN;
@@ -794,7 +794,7 @@ parameter BSIGN_REG = 1'b0;
 parameter MULT_RESET_MODE = "SYNC"; 
 endmodule
 
-module MULTALU36X18 (...);
+module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
 input  [17:0] A;
 input  [35:0] B;
 input  [53:0] C;
@@ -819,7 +819,7 @@ parameter MULTALU36X18_MODE = 0;
 parameter C_ADD_SUB = 1'b0; 
 endmodule
 
-module MULTADDALU18X18 (...);
+module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
 input [17:0] A0;
 input [17:0] B0;
 input [17:0] A1;
@@ -857,7 +857,7 @@ parameter MULTADDALU18X18_MODE = 0;
 parameter MULT_RESET_MODE = "SYNC";
 endmodule
 
-module MULTALU18X18 (...);
+module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO);
 input [17:0] A, B;
 input CLK,CE,RESET;
 input ASIGN, BSIGN;
@@ -883,7 +883,7 @@ parameter C_ADD_SUB = 1'b0;
 parameter MULTALU18X18_MODE = 0; 
 endmodule
 
-module ALU54D (...);
+module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
 input [53:0] A, B;
 input ASIGN,BSIGN;
 input ACCLOAD;
@@ -903,19 +903,19 @@ parameter ALUD_MODE = 0;
 parameter ALU_RESET_MODE = "SYNC";
 endmodule
 
-module BUFG (...);
+module BUFG(O, I);
 output O;
 input I;
 endmodule
 
 
-module BUFS (...);
+module BUFS(O, I);
 output O;
 input I;
 endmodule
 
 
-module PLL (...);
+module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
 input CLKIN;
 input CLKFB;
 input RESET; 
@@ -956,39 +956,39 @@ parameter CLKOUTD3_SRC = "CLKOUT";
 parameter DEVICE = "GW1N-4";
 endmodule
 
-module TLVDS_IBUF (...);
+module TLVDS_IBUF(O, I, IB);
 output O;
 input  I, IB;
 endmodule
 
-module TLVDS_TBUF (...);
+module TLVDS_TBUF(O, OB, I, OEN);
 output O, OB;
 input  I, OEN;
 endmodule
 
-module TLVDS_IOBUF (...);
+module TLVDS_IOBUF(O, IO, IOB, I, OEN);
 output   O;
 inout IO, IOB;
 input I, OEN;
 endmodule
 
-module ELVDS_IBUF (...);
+module ELVDS_IBUF(O, I, IB);
 output O;
 input  I, IB;
 endmodule
 
-module ELVDS_TBUF (...);
+module ELVDS_TBUF(O, OB, I, OEN);
 output O, OB;
 input  I, OEN;
 endmodule
 
-module ELVDS_IOBUF (...);
+module ELVDS_IOBUF(O, IO, IOB, I, OEN);
 output   O;
 inout IO, IOB;
 input I, OEN;
 endmodule
 
-module MIPI_IBUF (...);
+module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN);
 output OH, OL, OB;
 inout IO, IOB;
 input  I, IB;
@@ -996,40 +996,40 @@ input OEN, OENB;
 input HSREN;
 endmodule
 
-module MIPI_IBUF_HS (...);
+module MIPI_IBUF_HS(OH, I, IB);
 output OH;
 input  I, IB;
 endmodule
 
-module MIPI_IBUF_LP (...);
+module MIPI_IBUF_LP(OL, OB, I, IB);
 output OL;
 output OB;
 input  I;
 input IB;
 endmodule
 
-module MIPI_OBUF (...);
+module MIPI_OBUF(O, OB, I, IB, MODESEL);
 output O, OB;
 input  I, IB, MODESEL;
 endmodule
 
-module MIPI_OBUF_A (...);
+module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL);
 output O, OB;
 input  I, IB, IL, MODESEL;
 endmodule
 
-module ELVDS_IBUF_MIPI (...);
+module ELVDS_IBUF_MIPI(OH, OL, I, IB);
 output OH, OL;
 input  I, IB;
 endmodule
 
-module I3C_IOBUF (...);
+module I3C_IOBUF(O, IO, I, MODESEL);
 output O;
 inout IO;
 input  I, MODESEL;
 endmodule
 
-module CLKDIV (...);
+module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT);
 input HCLKIN;
 input RESETN;
 input CALIB;
@@ -1038,12 +1038,12 @@ parameter DIV_MODE = "2";
 parameter GSREN = "false"; 
 endmodule
 
-module DHCEN (...);
+module DHCEN(CLKIN, CE, CLKOUT);
 input CLKIN,CE;
 output CLKOUT;
 endmodule
 
-module DLLDLY (...);
+module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
 input CLKIN;
 input [7:0] DLLSTEP;
 input DIR,LOADN,MOVE;
@@ -1054,7 +1054,7 @@ parameter DLY_SIGN = 1'b0;
 parameter DLY_ADJ = 0; 
 endmodule
 
-module FLASH96K (...);
+module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT);
 input [5:0] RA,CA,PA;
 input [3:0] MODE;
 input [1:0] SEQ;
@@ -1065,7 +1065,7 @@ input [31:0] DIN;
 output [31:0] DOUT;
 endmodule
 
-module FLASH256K (...);
+module FLASH256K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
 input[6:0]XADR;
 input[5:0]YADR;
 input XE,YE,SE;
@@ -1087,7 +1087,7 @@ parameter IDLE    =  4'd0,
 		  RD_S2   =  4'd12;		  
 endmodule
 
-module FLASH608K (...);
+module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
 input[8:0]XADR;
 input[5:0]YADR;
 input XE,YE,SE;
@@ -1109,31 +1109,31 @@ parameter IDLE    =  4'd0,
 		  RD_S2   =  4'd12;
 endmodule
 
-module DCS (...);
+module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
 input CLK0, CLK1, CLK2, CLK3, SELFORCE;
 input [3:0] CLKSEL;
 output CLKOUT;
   parameter DCS_MODE = "RISING";  
 endmodule
 
-module DQCE (...);
+module DQCE(CLKIN, CE, CLKOUT);
 input CLKIN;
 input CE;
 output CLKOUT;
 endmodule
 
-module CLKDIV2 (...);
+module CLKDIV2(HCLKIN, RESETN, CLKOUT);
 parameter GSREN = "false"; 
 input HCLKIN, RESETN;
 output CLKOUT;
 endmodule
 
-module DHCENC (...);
+module DHCENC(CLKIN, CE, CLKOUT, CLKOUTN);
 input CLKIN, CE;
 output CLKOUT, CLKOUTN;
 endmodule
 
-module FLASH64K (...);
+module FLASH64K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, SLEEP, DIN, DOUT);
 input[4:0]XADR;
 input[5:0]YADR;
 input XE,YE,SE;
@@ -1156,7 +1156,7 @@ parameter IDLE    =  4'd0,
 		  RD_S2   =  4'd12;		  
 endmodule
 
-module FLASH64KZ (...);
+module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
 input[4:0]XADR;
 input[5:0]YADR;
 input XE,YE,SE;

techlibs/gowin/cells_xtra_gw2a.v

@@ -1,41 +1,41 @@
 // Created by cells_xtra.py
 
 
-module LUT5 (...);
+module LUT5(I0, I1, I2, I3, I4, F);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
 output F;
 endmodule
 
 
-module LUT6 (...);
+module LUT6(I0, I1, I2, I3, I4, I5, F);
 parameter INIT = 64'h0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5;
 output F;
 endmodule
 
 
-module LUT7 (...);
+module LUT7(I0, I1, I2, I3, I4, I5, I6, F);
 parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5, I6;
 output F;
 endmodule
 
 
-module LUT8 (...);
+module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F);
 parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5, I6, I7;
 output F;
 endmodule
 
 
-module INV (...);
+module INV(I, O);
 input  I;
 output O;
 endmodule
 
 
-module IDDR_MEM (...);
+module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
 parameter GSREN = "false";  
 parameter LSREN = "true";    
 input D, ICLK, PCLK;
@@ -46,7 +46,7 @@ output  Q0,Q1;
 endmodule
 
 
-module ODDR_MEM (...);
+module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
 parameter TCLK_SOURCE = "DQSW"; 
@@ -57,7 +57,7 @@ output  Q0, Q1;
 endmodule
 
 
-module IDES4_MEM (...);
+module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3);
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
 input D, ICLK, FCLK, PCLK;
@@ -68,7 +68,7 @@ output Q0,Q1,Q2,Q3;
 endmodule
 
 
-module IDES8_MEM (...);
+module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
 input D, ICLK, FCLK, PCLK;
@@ -79,7 +79,7 @@ output  Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7;
 endmodule
 
 
-module OSER4_MEM (...);
+module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
 parameter HWL = "false";     
@@ -92,7 +92,7 @@ output  Q0,  Q1;
 endmodule
 
 
-module OSER8_MEM (...);
+module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
 parameter HWL = "false";    
@@ -105,7 +105,7 @@ output  Q0,  Q1;
 endmodule
 
 
-module IODELAY (...);
+module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
 parameter C_STATIC_DLY = 0; 
 input DI;
 input  SDTAP;
@@ -116,7 +116,7 @@ output DO;
 endmodule
 
 
-module IEM (...);
+module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
 parameter WINSIZE = "SMALL"; 
 parameter GSREN = "false"; 
 parameter LSREN = "true";    
@@ -125,14 +125,14 @@ output LAG, LEAD;
 endmodule
 
 
-module ROM16 (...);
+module ROM16(AD, DO);
 parameter INIT_0 = 16'h0000;
 input [3:0] AD;
 output DO;
 endmodule
 
 
-module ROM (...);
+module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
 parameter BLK_SEL = 3'b000;
@@ -211,7 +211,7 @@ output [31:0] DO;
 endmodule
 
 
-module ROMX9 (...);
+module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 36; 
 parameter BLK_SEL = 3'b000;
@@ -290,7 +290,7 @@ output [35:0] DO;
 endmodule
 
 
-module pROM (...);
+module pROM(CLK, CE, OCE, RESET, AD, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
 parameter RESET_MODE = "SYNC"; 
@@ -366,7 +366,7 @@ output [31:0] DO;
 endmodule
 
 
-module pROMX9 (...);
+module pROMX9(CLK, CE, OCE, RESET, AD, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 36; 
 parameter RESET_MODE = "SYNC"; 
@@ -442,7 +442,7 @@ output [35:0] DO;
 endmodule
 
 
-module SDPB (...);
+module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 32; 
 parameter BIT_WIDTH_1 = 32; 
@@ -523,7 +523,7 @@ output [31:0] DO;
 endmodule
 
 
-module SDPX9B (...);
+module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 36; 
 parameter BIT_WIDTH_1 = 36; 
@@ -604,7 +604,7 @@ output [35:0] DO;
 endmodule
 
 
-module DPB (...);
+module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
 parameter READ_MODE0 = 1'b0; 
 parameter READ_MODE1 = 1'b0; 
 parameter WRITE_MODE0 = 2'b00; 
@@ -689,7 +689,7 @@ output [15:0] DOA, DOB;
 endmodule
 
 
-module DPX9B (...);
+module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
 parameter READ_MODE0 = 1'b0; 
 parameter READ_MODE1 = 1'b0; 
 parameter WRITE_MODE0 = 2'b00; 
@@ -774,7 +774,7 @@ output [17:0] DOA, DOB;
 endmodule
 
 
-module PADD18 (...);
+module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
 input  [17:0] A;
 input  [17:0] B;
 input  ASEL;
@@ -790,7 +790,7 @@ parameter BSEL_MODE = 1'b1;
 parameter SOREG = 1'b0;
 endmodule
 
-module PADD9 (...);
+module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
 input  [8:0] A;
 input  [8:0] B;
 input  ASEL;
@@ -806,7 +806,7 @@ parameter BSEL_MODE = 1'b1;
 parameter SOREG = 1'b0;
 endmodule
 
-module MULT9X9 (...);
+module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
 input  [8:0] A,SIA;
 input  [8:0] B,SIB;
 input  ASIGN,BSIGN;
@@ -826,7 +826,7 @@ parameter SOA_REG = 1'b0;
 parameter MULT_RESET_MODE = "SYNC"; 
 endmodule
 
-module MULT18X18 (...);
+module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
 input  [17:0] A,SIA;
 input  [17:0] B,SIB;
 input  ASIGN,BSIGN;
@@ -846,7 +846,7 @@ parameter SOA_REG = 1'b0;
 parameter MULT_RESET_MODE = "SYNC"; 
 endmodule
 
-module MULT36X36 (...);
+module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
 input  [35:0] A;
 input  [35:0] B;
 input  ASIGN,BSIGN;
@@ -864,7 +864,7 @@ parameter BSIGN_REG = 1'b0;
 parameter MULT_RESET_MODE = "SYNC"; 
 endmodule
 
-module MULTALU36X18 (...);
+module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
 input  [17:0] A;
 input  [35:0] B;
 input  [53:0] C;
@@ -889,7 +889,7 @@ parameter MULTALU36X18_MODE = 0;
 parameter C_ADD_SUB = 1'b0; 
 endmodule
 
-module MULTADDALU18X18 (...);
+module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
 input [17:0] A0;
 input [17:0] B0;
 input [17:0] A1;
@@ -927,7 +927,7 @@ parameter MULTADDALU18X18_MODE = 0;
 parameter MULT_RESET_MODE = "SYNC";
 endmodule
 
-module MULTALU18X18 (...);
+module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO);
 input [17:0] A, B;
 input CLK,CE,RESET;
 input ASIGN, BSIGN;
@@ -953,7 +953,7 @@ parameter C_ADD_SUB = 1'b0;
 parameter MULTALU18X18_MODE = 0; 
 endmodule
 
-module ALU54D (...);
+module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
 input [53:0] A, B;
 input ASIGN,BSIGN;
 input ACCLOAD;
@@ -973,19 +973,19 @@ parameter ALUD_MODE = 0;
 parameter ALU_RESET_MODE = "SYNC";
 endmodule
 
-module BUFG (...);
+module BUFG(O, I);
 output O;
 input I;
 endmodule
 
 
-module BUFS (...);
+module BUFS(O, I);
 output O;
 input I;
 endmodule
 
 
-module PLL (...);
+module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
 input CLKIN;
 input CLKFB;
 input RESET;
@@ -1026,39 +1026,39 @@ parameter CLKOUTD3_SRC = "CLKOUT";
 parameter DEVICE = "GW2A-18";
 endmodule
 
-module TLVDS_IBUF (...);
+module TLVDS_IBUF(O, I, IB);
 output O;
 input  I, IB;
 endmodule
 
-module TLVDS_TBUF (...);
+module TLVDS_TBUF(O, OB, I, OEN);
 output O, OB;
 input  I, OEN;
 endmodule
 
-module TLVDS_IOBUF (...);
+module TLVDS_IOBUF(O, IO, IOB, I, OEN);
 output   O;
 inout IO, IOB;
 input I, OEN;
 endmodule
 
-module ELVDS_IBUF (...);
+module ELVDS_IBUF(O, I, IB);
 output O;
 input  I, IB;
 endmodule
 
-module ELVDS_TBUF (...);
+module ELVDS_TBUF(O, OB, I, OEN);
 output O, OB;
 input  I, OEN;
 endmodule
 
-module ELVDS_IOBUF (...);
+module ELVDS_IOBUF(O, IO, IOB, I, OEN);
 output   O;
 inout IO, IOB;
 input I, OEN;
 endmodule
 
-module CLKDIV (...);
+module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT);
 input HCLKIN;
 input RESETN;
 input CALIB;
@@ -1067,12 +1067,13 @@ parameter DIV_MODE = "2";
 parameter GSREN = "false"; 
 endmodule
 
-module DHCEN (...);
+module DHCEN(CLKIN, CE, CLKOUT);
 input CLKIN,CE;
 output CLKOUT;
 endmodule
 
-module DQS (...);
+module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID
+, RBURST, RFLAG, WFLAG);
 input DQSIN,PCLK,FCLK,RESET;
 input [3:0] READ;
 input [2:0] RCLKSEL;
@@ -1089,7 +1090,7 @@ output RVALID,RBURST, RFLAG, WFLAG;
     parameter GSREN = "false"; 
 endmodule
 
-module DLLDLY (...);
+module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
 input CLKIN;
 input [7:0] DLLSTEP;
 input DIR,LOADN,MOVE;
@@ -1100,67 +1101,67 @@ parameter DLY_SIGN = 1'b0;
 parameter DLY_ADJ = 0; 
 endmodule
 
-module DCS (...);
+module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
 input CLK0, CLK1, CLK2, CLK3, SELFORCE;
 input [3:0] CLKSEL;
 output CLKOUT;
   parameter DCS_MODE = "RISING";  
 endmodule
 
-module DQCE (...);
+module DQCE(CLKIN, CE, CLKOUT);
 input CLKIN;
 input CE;
 output CLKOUT;
 endmodule
 
-module CLKDIV2 (...);
+module CLKDIV2(HCLKIN, RESETN, CLKOUT);
 parameter GSREN = "false"; 
 input HCLKIN, RESETN;
 output CLKOUT;
 endmodule
 
-module IBUF_R (...);
+module IBUF_R(I, RTEN, O);
 input  I;
 input RTEN;
 output O;
 endmodule
 
-module IOBUF_R (...);
+module IOBUF_R(I, OEN, RTEN, O, IO);
 input I,OEN;
 input RTEN;
 output O;
 inout IO;
 endmodule
 
-module ELVDS_IBUF_R (...);
+module ELVDS_IBUF_R(O, I, IB, RTEN);
 output O;
 input I, IB;
 input RTEN;
 endmodule
 
-module ELVDS_IOBUF_R (...);
+module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN);
 output  O;
 inout IO, IOB;
 input I, OEN;
 input RTEN;
 endmodule
 
-module OTP (...);
+module OTP(CSB, SCLK, DOUT);
 input CSB, SCLK;
 output DOUT;
 endmodule
 
-module SAMB (...);
+module SAMB(SPIAD, LOADN_SPIAD);
 input [23:0] SPIAD;
 input LOADN_SPIAD;
 endmodule
 
-module ELVDS_IBUF_MIPI (...);
+module ELVDS_IBUF_MIPI(OH, OL, I, IB);
 output OH, OL;
 input  I, IB;
 endmodule
 
-module MIPI_IBUF (...);
+module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN);
 output OH, OL, OB;
 inout IO, IOB;
 input  I, IB;
@@ -1168,7 +1169,7 @@ input OEN, OENB;
 input HSREN;
 endmodule
 
-module I3C_IOBUF (...);
+module I3C_IOBUF(O, IO, I, MODESEL);
 output O;
 inout IO;
 input  I, MODESEL;

techlibs/gowin/cells_xtra_gw5a.v

@@ -1,75 +1,75 @@
 // Created by cells_xtra.py
 
 
-module LUT5 (...);
+module LUT5(I0, I1, I2, I3, I4, F);
 parameter INIT = 32'h00000000;
 input I0, I1, I2, I3, I4;
 output F;
 endmodule
 
 
-module LUT6 (...);
+module LUT6(I0, I1, I2, I3, I4, I5, F);
 parameter INIT = 64'h0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5;
 output F;
 endmodule
 
 
-module LUT7 (...);
+module LUT7(I0, I1, I2, I3, I4, I5, I6, F);
 parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5, I6;
 output F;
 endmodule
 
 
-module LUT8 (...);
+module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F);
 parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
 input I0, I1, I2, I3, I4, I5, I6, I7;
 output F;
 endmodule
 
 
-module ROM16 (...);
+module ROM16(AD, DO);
 parameter INIT_0 = 16'h0000;
 input [3:0] AD;
 output DO;
 endmodule
 
 
-module INV (...);
+module INV(I, O);
 input  I;
 output O;
 endmodule
 
 
-module TLVDS_IBUF (...);
+module TLVDS_IBUF(O, I, IB);
 output O;
 input  I, IB;
 endmodule
 
-module TLVDS_TBUF (...);
+module TLVDS_TBUF(O, OB, I, OEN);
 output O, OB;
 input  I, OEN;
 endmodule
 
-module TLVDS_IOBUF (...);
+module TLVDS_IOBUF(O, IO, IOB, I, OEN);
 output   O;
 inout IO, IOB;
 input I, OEN;
 endmodule
 
-module ELVDS_TBUF (...);
+module ELVDS_TBUF(O, OB, I, OEN);
 output O, OB;
 input  I, OEN;
 endmodule
 
-module ELVDS_IOBUF (...);
+module ELVDS_IOBUF(O, IO, IOB, I, OEN);
 output   O;
 inout IO, IOB;
 input I, OEN;
 endmodule
 
-module MIPI_IBUF (...);
+module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSEN, HSREN);
 output OH, OL, OB;
 inout IO, IOB;
 input  I, IB;
@@ -77,32 +77,33 @@ input OEN, OENB;
 input HSEN, HSREN;
 endmodule
 
-module MIPI_OBUF_A (...);
+module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL, IO, IOB, OEN, OENB);
 output O, OB;
 input  I, IB, IL, MODESEL;
 inout IO, IOB;
 input OEN, OENB;
 endmodule
 
-module ELVDS_IOBUF_R (...);
+module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN);
 output  O;
 inout IO, IOB;
 input I, OEN;
 input RTEN;
 endmodule
 
-module I3C_IOBUF (...);
+module I3C_IOBUF(O, IO, I, MODESEL);
 output O;
 inout IO;
 input  I, MODESEL;
 endmodule
 
-module TLVDS_IBUF_ADC (...);
+module TLVDS_IBUF_ADC(I, IB, ADCEN);
 input I, IB;
 input ADCEN;
 endmodule
 
-module MIPI_CPHY_IBUF (...);
+module MIPI_CPHY_IBUF(OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2, IO0, IOB0, IO1, IOB1, IO2, IOB2, I0, IB0, I1, IB1, I2, IB2
+, OEN, OENB, HSEN);
 output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;
 inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
 input  I0, IB0, I1, IB1, I2, IB2;
@@ -110,14 +111,15 @@ input OEN, OENB;
 input HSEN;
 endmodule
 
-module MIPI_CPHY_OBUF (...);
+module MIPI_CPHY_OBUF(O0, OB0, O1, OB1, O2, OB2, I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2, IO0, IOB0, IO1, IOB1, IO2, IOB2
+, OEN, OENB, MODESEL, VCOME);
 output O0, OB0, O1, OB1, O2, OB2;
 input  I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;
 inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
 input OEN, OENB, MODESEL, VCOME;
 endmodule
 
-module SDPB (...);
+module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 32; 
 parameter BIT_WIDTH_1 = 32; 
@@ -198,7 +200,7 @@ output [31:0] DO;
 endmodule
 
 
-module SDPX9B (...);
+module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH_0 = 36; 
 parameter BIT_WIDTH_1 = 36; 
@@ -279,7 +281,7 @@ output [35:0] DO;
 endmodule
 
 
-module DPB (...);
+module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
 parameter READ_MODE0 = 1'b0; 
 parameter READ_MODE1 = 1'b0; 
 parameter WRITE_MODE0 = 2'b00; 
@@ -364,7 +366,7 @@ output [15:0] DOA, DOB;
 endmodule
 
 
-module DPX9B (...);
+module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
 parameter READ_MODE0 = 1'b0; 
 parameter READ_MODE1 = 1'b0; 
 parameter WRITE_MODE0 = 2'b00; 
@@ -449,7 +451,7 @@ output [17:0] DOA, DOB;
 endmodule
 
 
-module pROM (...);
+module pROM(CLK, CE, OCE, RESET, AD, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 32; 
 parameter RESET_MODE = "SYNC"; 
@@ -525,7 +527,7 @@ output [31:0] DO;
 endmodule
 
 
-module pROMX9 (...);
+module pROMX9(CLK, CE, OCE, RESET, AD, DO);
 parameter READ_MODE = 1'b0; 
 parameter BIT_WIDTH = 36; 
 parameter RESET_MODE = "SYNC"; 
@@ -601,7 +603,7 @@ output [35:0] DO;
 endmodule
 
 
-module SDP36KE (...);
+module SDP36KE(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, DIP, BLKSELA, BLKSELB, DECCI, SECCI, DO, DOP, DECCO, SECCO, ECCP);
 parameter ECC_WRITE_EN="TRUE"; 
 parameter ECC_READ_EN="TRUE"; 
 parameter READ_MODE = 1'b0; 
@@ -768,7 +770,7 @@ output [7:0] ECCP;
 endmodule
 
 
-module SDP136K (...);
+module SDP136K(CLKA, CLKB, WE, RE, ADA, ADB, DI, DO);
 input CLKA, CLKB;
 input WE, RE;
 input [10:0] ADA, ADB;
@@ -776,7 +778,7 @@ input [67:0] DI;
 output [67:0] DO;
 endmodule
 
-module MULTADDALU12X12 (...);
+module MULTADDALU12X12(DOUT, CASO, A0, B0, A1, B1, CASI, ACCSEL, CASISEL, ADDSUB, CLK, CE, RESET);
 parameter A0REG_CLK = "BYPASS"; 
 parameter A0REG_CE = "CE0"; 
 parameter A0REG_RESET = "RESET0"; 
@@ -842,7 +844,7 @@ input  [1:0] ADDSUB;
 input  [1:0] CLK, CE, RESET;
 endmodule
 
-module MULTALU27X18 (...);
+module MULTALU27X18(DOUT, CASO, SOA, A, SIA, B, C, D, CASI, ACCSEL, PSEL, ASEL, PADDSUB, CSEL, CASISEL, ADDSUB, CLK, CE, RESET);
 parameter AREG_CLK = "BYPASS"; 
 parameter AREG_CE = "CE0"; 
 parameter AREG_RESET = "RESET0"; 
@@ -937,7 +939,7 @@ input  [1:0] ADDSUB;
 input  [1:0] CLK, CE, RESET;
 endmodule
 
-module MULT12X12 (...);
+module MULT12X12(DOUT, A, B, CLK, CE, RESET);
 parameter AREG_CLK = "BYPASS"; 
 parameter AREG_CE = "CE0"; 
 parameter AREG_RESET = "RESET0"; 
@@ -956,7 +958,7 @@ input  [11:0] A, B;
 input  [1:0] CLK, CE, RESET;
 endmodule
 
-module MULT27X36 (...);
+module MULT27X36(DOUT, A, B, D, CLK, CE, RESET, PSEL, PADDSUB);
 parameter AREG_CLK = "BYPASS"; 
 parameter AREG_CE = "CE0"; 
 parameter AREG_RESET = "RESET0"; 
@@ -992,7 +994,7 @@ input  PSEL;
 input  PADDSUB;
 endmodule
 
-module MULTACC (...);
+module MULTACC(DATAO, CASO, CE, CLK, COFFIN0, COFFIN1, COFFIN2, DATAIN0, DATAIN1, DATAIN2, RSTN, CASI);
 output  [23:0] DATAO, CASO;
 input CE, CLK;
 input [5:0] COFFIN0, COFFIN1, COFFIN2;
@@ -1010,7 +1012,7 @@ parameter CASI_EN = "FALSE";
 parameter CASO_EN = "FALSE"; 
 endmodule
 
-module IDDR_MEM (...);
+module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
 input D, ICLK, PCLK;
 input [2:0] WADDR;
 input [2:0] RADDR;
@@ -1019,7 +1021,7 @@ output  Q0,Q1;
 endmodule
 
 
-module ODDR_MEM (...);
+module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
 parameter TCLK_SOURCE = "DQSW"; 
 parameter TXCLK_POL = 1'b0; 
 input D0, D1;
@@ -1028,7 +1030,7 @@ output  Q0, Q1;
 endmodule
 
 
-module IDES4_MEM (...);
+module IDES4_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3);
 input PCLK, D, ICLK, FCLK, RESET, CALIB;
 input [2:0] WADDR;
 input [2:0] RADDR;
@@ -1036,7 +1038,7 @@ output Q0,Q1,Q2,Q3;
 endmodule
 
 
-module IDES8_MEM (...);
+module IDES8_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
 input PCLK, D, ICLK, FCLK, RESET, CALIB;
 input [2:0] WADDR;
 input [2:0] RADDR;
@@ -1044,19 +1046,20 @@ output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;
 endmodule
 
 
-module IDES14 (...);
+module IDES14(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13);
 input D, FCLK, PCLK, CALIB,RESET;
 output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13;
 endmodule
 
 
-module IDES32 (...);
+module IDES32(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15
+, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31);
 input D, FCLK, PCLK, CALIB,RESET;
 output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31;
 endmodule
 
 
-module OSER4_MEM (...);
+module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
 parameter HWL = "false";     
 parameter TCLK_SOURCE = "DQSW"; 
 parameter TXCLK_POL = 1'b0; 
@@ -1067,7 +1070,7 @@ output  Q0,  Q1;
 endmodule
 
 
-module OSER8_MEM (...);
+module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
 parameter HWL = "false";    
 parameter TCLK_SOURCE = "DQSW"; 
 parameter TXCLK_POL = 1'b0; 
@@ -1078,13 +1081,13 @@ output  Q0,  Q1;
 endmodule
 
 
-module OSER14 (...);
+module OSER14(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, PCLK, FCLK, RESET, Q);
 input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13;
 input PCLK, FCLK, RESET;
 output  Q;
 endmodule
 
-module IODELAY (...);
+module IODELAY(DI, SDTAP, VALUE, DLYSTEP, DF, DO);
 parameter C_STATIC_DLY = 0; 
 parameter DYN_DLY_EN = "FALSE";
 parameter ADAPT_EN = "FALSE";
@@ -1097,7 +1100,7 @@ output DO;
 endmodule
 
 
-module OSIDES32 (...);
+module OSIDES32(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, SDTAP0, SDTAP1, VALUE0, VALUE1, DLYSTEP0, DLYSTEP1);
 output [31:0] Q;
 input D;
 input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
@@ -1114,7 +1117,8 @@ parameter DYN_DLY_EN_1 = "FALSE";
 parameter ADAPT_EN_1 = "FALSE";
 endmodule
 
-module OSIDES64 (...);
+module OSIDES64(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, DF2, DF3, SDTAP0, SDTAP1, SDTAP2, SDTAP3, VALUE0, VALUE1, VALUE2, VALUE3, DLYSTEP0
+, DLYSTEP1, DLYSTEP2, DLYSTEP3);
 output [63:0] Q;
 input D;
 input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
@@ -1137,20 +1141,20 @@ parameter DYN_DLY_EN_3 = "FALSE";
 parameter ADAPT_EN_3 = "FALSE";
 endmodule
 
-module DCE (...);
+module DCE(CLKIN, CE, CLKOUT);
 input CLKIN;
 input CE;
 output CLKOUT;
 endmodule
 
-module DCS (...);
+module DCS(CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE, CLKSEL, CLKOUT);
 input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE;
 input [3:0] CLKSEL;
 output CLKOUT;
 parameter DCS_MODE = "RISING";  
 endmodule
 
-module DDRDLL (...);
+module DDRDLL(CLKIN, STOP, UPDNCNTL, RESET, STEP, LOCK);
 input CLKIN;
 input STOP;
 input UPDNCNTL;
@@ -1163,7 +1167,7 @@ parameter SCAL_EN = "TRUE";
 parameter DIV_SEL = 1'b0; 
 endmodule
 
-module DLLDLY (...);
+module DLLDLY(CLKIN, DLLSTEP, CSTEP, LOADN, MOVE, CLKOUT, FLAG);
 input CLKIN;
 input [7:0] DLLSTEP, CSTEP;
 input LOADN,MOVE;
@@ -1176,7 +1180,7 @@ parameter ADAPT_EN = "FALSE";
 parameter STEP_SEL = 1'b0;
 endmodule
 
-module CLKDIV (...);
+module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT);
 input HCLKIN;
 input RESETN;
 input CALIB;
@@ -1184,24 +1188,24 @@ output CLKOUT;
 parameter DIV_MODE = "2"; 
 endmodule
 
-module CLKDIV2 (...);
+module CLKDIV2(HCLKIN, RESETN, CLKOUT);
 input HCLKIN, RESETN;
 output CLKOUT;
 endmodule
 
-module DHCE (...);
+module DHCE(CLKIN, CEN, CLKOUT);
 input CLKIN;
 input CEN;
 output CLKOUT;
 endmodule
 
-module OSCA (...);
+module OSCA(OSCOUT, OSCEN);
 parameter  FREQ_DIV = 100; 
 output OSCOUT;
 input OSCEN;
 endmodule
 
-module OSCB (...);
+module OSCB(OSCOUT, OSCREF, OSCEN, FMODE, RTRIM, RTCTRIM);
 parameter FREQ_MODE = "25"; 
 parameter FREQ_DIV = 10; 
 parameter DYN_TRIM_EN = "FALSE"; 
@@ -1212,7 +1216,9 @@ input [7:0] RTRIM;
 input [5:0] RTCTRIM; 
 endmodule
 
-module PLL (...);
+module PLL(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, FBDSEL, IDSEL, MDSEL, MDSEL_FRAC, ODSEL0, ODSEL0_FRAC, ODSEL1, ODSEL2, ODSEL3, ODSEL4, ODSEL5, ODSEL6, DT0, DT1, DT2
+, DT3, ICPSEL, LPFRES, LPFCAP, PSSEL, PSDIR, PSPULSE, ENCLK0, ENCLK1, ENCLK2, ENCLK3, ENCLK4, ENCLK5, ENCLK6, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, LOCK, CLKOUT0, CLKOUT1
+, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT);
 input CLKIN;
 input CLKFB;
 input RESET;
@@ -1354,7 +1360,8 @@ parameter LPF_CAP = 2'b00;
 parameter SSC_EN = "FALSE";
 endmodule
 
-module PLLA (...);
+module PLLA(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, PSSEL, PSDIR, PSPULSE, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, MDCLK, MDOPC, MDAINC, MDWDI, MDRDO, LOCK, CLKOUT0, CLKOUT1
+, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT);
 input CLKIN;
 input CLKFB;
 input RESET;
@@ -1462,7 +1469,14 @@ parameter LPF_CAP = 2'b00;
 parameter SSC_EN = "FALSE";
 endmodule
 
-module AE350_SOC (...);
+module AE350_SOC(POR_N, HW_RSTN, CORE_CLK, DDR_CLK, AHB_CLK, APB_CLK, DBG_TCK, RTC_CLK, CORE_CE, AXI_CE, DDR_CE, AHB_CE, APB_CE, APB2AHB_CE, SCAN_TEST, SCAN_EN, PRESETN, HRESETN, DDR_RSTN, GP_INT, DMA_REQ
+, DMA_ACK, CORE0_WFI_MODE, WAKEUP_IN, RTC_WAKEUP, TEST_CLK, TEST_MODE, TEST_RSTN, ROM_HADDR, ROM_HRDATA, ROM_HREADY, ROM_HRESP, ROM_HTRANS, ROM_HWRITE, APB_PADDR, APB_PENABLE, APB_PRDATA, APB_PREADY, APB_PSEL, APB_PWDATA, APB_PWRITE, APB_PSLVERR
+, APB_PPROT, APB_PSTRB, EXTS_HRDATA, EXTS_HREADYIN, EXTS_HRESP, EXTS_HADDR, EXTS_HBURST, EXTS_HPROT, EXTS_HSEL, EXTS_HSIZE, EXTS_HTRANS, EXTS_HWDATA, EXTS_HWRITE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL
+, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE, DDR_HADDR, DDR_HBURST, DDR_HPROT, DDR_HRDATA, DDR_HREADY, DDR_HRESP, DDR_HSIZE, DDR_HTRANS, DDR_HWDATA, DDR_HWRITE, TMS_IN, TRST_IN, TDI_IN, TDO_OUT, TDO_OE, SPI2_HOLDN_IN, SPI2_WPN_IN
+, SPI2_CLK_IN, SPI2_CSN_IN, SPI2_MISO_IN, SPI2_MOSI_IN, SPI2_HOLDN_OUT, SPI2_HOLDN_OE, SPI2_WPN_OUT, SPI2_WPN_OE, SPI2_CLK_OUT, SPI2_CLK_OE, SPI2_CSN_OUT, SPI2_CSN_OE, SPI2_MISO_OUT, SPI2_MISO_OE, SPI2_MOSI_OUT, SPI2_MOSI_OE, I2C_SCL_IN, I2C_SDA_IN, I2C_SCL, I2C_SDA, UART1_TXD
+, UART1_RTSN, UART1_RXD, UART1_CTSN, UART1_DSRN, UART1_DCDN, UART1_RIN, UART1_DTRN, UART1_OUT1N, UART1_OUT2N, UART2_TXD, UART2_RTSN, UART2_RXD, UART2_CTSN, UART2_DCDN, UART2_DSRN, UART2_RIN, UART2_DTRN, UART2_OUT1N, UART2_OUT2N, CH0_PWM, CH0_PWMOE
+, CH1_PWM, CH1_PWMOE, CH2_PWM, CH2_PWMOE, CH3_PWM, CH3_PWMOE, GPIO_IN, GPIO_OE, GPIO_OUT, SCAN_IN, INTEG_TCK, INTEG_TDI, INTEG_TMS, INTEG_TRST, INTEG_TDO, SCAN_OUT, PGEN_CHAIN_I, PRDYN_CHAIN_O, EMA, EMAW, EMAS
+, RET1N, RET2N);
 input               POR_N;
 input               HW_RSTN;
 input               CORE_CLK;
@@ -1614,7 +1628,8 @@ input		RET1N;
 input		RET2N;
 endmodule
 
-module AE350_RAM (...);
+module AE350_RAM(POR_N, HW_RSTN, CORE_CLK, AHB_CLK, APB_CLK, RTC_CLK, CORE_CE, AXI_CE, AHB_CE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE
+, EMA, EMAW, EMAS, RET1N, RET2N);
 input               POR_N;
 input               HW_RSTN;
 input               CORE_CLK;
@@ -1643,20 +1658,20 @@ input		RET1N;
 input		RET2N;
 endmodule
 
-module SAMB (...);
+module SAMB(SPIAD, LOAD, ADWSEL);
 parameter MODE = 2'b00; 
 input [23:0] SPIAD;
 input LOAD;
 input ADWSEL; 
 endmodule
 
-module OTP (...);
+module OTP(CLK, READ, SHIFT, DOUT);
 parameter MODE = 2'b01; 
 input CLK, READ, SHIFT;
 output DOUT;
 endmodule
 
-module CMSER (...);
+module CMSER(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERRINJECT, ERRINJLOC);
 output RUNNING;
 output CRCERR;
 output CRCDONE;
@@ -1675,7 +1690,7 @@ input ERRINJECT;
 input [6:0] ERRINJLOC;
 endmodule
 
-module CMSERA (...);
+module CMSERA(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERR0LOC, ERR1LOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC);
 output RUNNING;
 output CRCERR;
 output CRCDONE;
@@ -1695,7 +1710,7 @@ input ERR0INJECT,ERR1INJECT;
 input [6:0] ERRINJ0LOC,ERRINJ1LOC;
 endmodule
 
-module CMSERB (...);
+module CMSERB(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC);
 output RUNNING;
 output CRCERR;
 output CRCDONE;
@@ -1714,13 +1729,13 @@ input ERR0INJECT,ERR1INJECT;
 input [6:0] ERRINJ0LOC,ERRINJ1LOC;
 endmodule
 
-module SAMBA (...);
+module SAMBA(SPIAD, LOAD);
 parameter MODE = 2'b00; 
 input SPIAD;
 input LOAD;
 endmodule
 
-module LICD (...);
+module LICD();
     parameter   STAGE_NUM = 2'b00;        
     parameter   ENCDEC_NUM = 2'b00;       
     parameter   CODE_WIDTH = 2'b00;       
@@ -1728,7 +1743,13 @@ module LICD (...);
     parameter   INTERLEAVE_MODE = 3'b000;  
 endmodule
 
-module MIPI_DPHY (...);
+module MIPI_DPHY(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N
+, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1
+, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0
+, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1
+, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK, D1LN_DESKEW_DONE
+, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK
+, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK);
 output RX_CLK_O, TX_CLK_O;
 output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
 output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
@@ -2024,7 +2045,13 @@ parameter        TEST_P_IMP_LN3                 = 1'b0 ;
 parameter        TEST_P_IMP_LNCK                = 1'b0 ;   
 endmodule
 
-module MIPI_DPHYA (...);
+module MIPI_DPHYA(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N
+, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1
+, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0
+, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1
+, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, SPLL_CKN, SPLL_CKP, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3
+, ALPEDO_LANECK, D1LN_DESKEW_DONE, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2
+, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK);
 output RX_CLK_O, TX_CLK_O;
 output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
 output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
@@ -2323,7 +2350,12 @@ parameter        TEST_P_IMP_LN3                 = 1'b0 ;
 parameter        TEST_P_IMP_LNCK                = 1'b0 ;   
 endmodule
 
-module MIPI_CPHY (...);
+module MIPI_CPHY(D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD, D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR, D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA, D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O
+, HSTX_FIFO_AE, HSTX_FIFO_AF, HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR, RX_CLK_MUXED, TX_CLK_1X_O, DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C, MDRP_RDATA, D0A, D0B, D0C, D1A, D1B
+, D1C, D2A, D2B, D2C, D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN, D0LN_HSTX_DATA, D1LN_HSTX_DATA, D2LN_HSTX_DATA, D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD, D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS, D0LN_RX_CLK_1X_I, D1LN_RX_CLK_1X_I
+, D2LN_RX_CLK_1X_I, D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N, HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2, MDRP_A_D_I, MDRP_A_INC_I, MDRP_CLK_I, MDRP_OPCODE_I, PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX
+, ARST_RXLN0, ARST_RXLN1, ARST_RXLN2, ARSTN_TX, RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2, TX_CLK_1X_I, TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2, TXHCLK_EN, DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2
+, GPLL_CK0, GPLL_CK90, GPLL_CK180, GPLL_CK270, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP);
 output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;
 output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;
 output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;
@@ -2455,29 +2487,30 @@ parameter EQ_PBIAS_LN2 = 4'b0100;
 parameter EQ_ZLD_LN2 = 4'b1000; 
 endmodule
 
-module GTR12_QUAD (...);
+module GTR12_QUAD();
     parameter POSITION = "Q0";
 endmodule
 
-module GTR12_UPAR (...);
+module GTR12_UPAR();
 endmodule
 
-module GTR12_PMAC (...);
+module GTR12_PMAC();
 endmodule
 
-module GTR12_QUADA (...);
+module GTR12_QUADA();
 endmodule
 
-module GTR12_UPARA (...);
+module GTR12_UPARA();
 endmodule
 
-module GTR12_PMACA (...);
+module GTR12_PMACA();
 endmodule
 
-module GTR12_QUADB (...);
+module GTR12_QUADB();
 endmodule
 
-module DQS (...);
+module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID
+, RBURST, RFLAG, WFLAG);
 input DQSIN,PCLK,FCLK,RESET;
 input [3:0] READ;
 input [2:0] RCLKSEL;

techlibs/gowin/synth_gowin.cc

@@ -311,6 +311,7 @@ struct SynthGowinPass : public ScriptPass
 
 		if (check_label("map_luts"))
 		{
+			run("sort");
 			if (nowidelut && abc9) {
 				run("read_verilog -icells -lib -specify +/abc9_model.v");
 				run("abc9 -maxlut 4 -W 500");

techlibs/lattice/cells_bb_ecp5.v

@@ -1,24 +1,29 @@
 // Created by cells_xtra.py from Lattice models
 
 (* blackbox *) (* keep *)
-module GSR (...);
+module GSR(GSR);
     input GSR;
 endmodule
 
 (* blackbox *)
-module PUR (...);
+module PUR(PUR);
     parameter RST_PULSE = 1;
     input PUR;
 endmodule
 
 (* blackbox *) (* keep *)
-module SGSR (...);
+module SGSR(GSR, CLK);
     input GSR;
     input CLK;
 endmodule
 
 (* blackbox *)
-module PDPW16KD (...);
+module PDPW16KD(DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15
+, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6, ADW5, ADW4, ADW3
+, ADW2, ADW1, ADW0, BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
+, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27
+, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6
+, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter CLKRMUX = "CLKR";
     parameter CLKWMUX = "CLKW";
     parameter DATA_WIDTH_W = 36;
@@ -208,7 +213,18 @@ module PDPW16KD (...);
 endmodule
 
 (* blackbox *)
-module MULT18X18D (...);
+module MULT18X18D(A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, B17, B16, B15
+, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, C17, C16, C15, C14, C13, C12
+, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, CLK3, CLK2, CLK1, CLK0, CE3
+, CE2, CE1, CE0, RST3, RST2, RST1, RST0, SRIA17, SRIA16, SRIA15, SRIA14, SRIA13, SRIA12, SRIA11, SRIA10, SRIA9, SRIA8, SRIA7, SRIA6, SRIA5, SRIA4
+, SRIA3, SRIA2, SRIA1, SRIA0, SRIB17, SRIB16, SRIB15, SRIB14, SRIB13, SRIB12, SRIB11, SRIB10, SRIB9, SRIB8, SRIB7, SRIB6, SRIB5, SRIB4, SRIB3, SRIB2, SRIB1
+, SRIB0, SROA17, SROA16, SROA15, SROA14, SROA13, SROA12, SROA11, SROA10, SROA9, SROA8, SROA7, SROA6, SROA5, SROA4, SROA3, SROA2, SROA1, SROA0, SROB17, SROB16
+, SROB15, SROB14, SROB13, SROB12, SROB11, SROB10, SROB9, SROB8, SROB7, SROB6, SROB5, SROB4, SROB3, SROB2, SROB1, SROB0, ROA17, ROA16, ROA15, ROA14, ROA13
+, ROA12, ROA11, ROA10, ROA9, ROA8, ROA7, ROA6, ROA5, ROA4, ROA3, ROA2, ROA1, ROA0, ROB17, ROB16, ROB15, ROB14, ROB13, ROB12, ROB11, ROB10
+, ROB9, ROB8, ROB7, ROB6, ROB5, ROB4, ROB3, ROB2, ROB1, ROB0, ROC17, ROC16, ROC15, ROC14, ROC13, ROC12, ROC11, ROC10, ROC9, ROC8, ROC7
+, ROC6, ROC5, ROC4, ROC3, ROC2, ROC1, ROC0, P35, P34, P33, P32, P31, P30, P29, P28, P27, P26, P25, P24, P23, P22
+, P21, P20, P19, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1
+, P0, SIGNEDP);
     parameter REG_INPUTA_CLK = "NONE";
     parameter REG_INPUTA_CE = "CE0";
     parameter REG_INPUTA_RST = "RST0";
@@ -470,7 +486,28 @@ module MULT18X18D (...);
 endmodule
 
 (* blackbox *)
-module ALU54B (...);
+module ALU54B(CE3, CE2, CE1, CE0, CLK3, CLK2, CLK1, CLK0, RST3, RST2, RST1, RST0, SIGNEDIA, SIGNEDIB, SIGNEDCIN, A35, A34, A33, A32, A31, A30
+, A29, A28, A27, A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9
+, A8, A7, A6, A5, A4, A3, A2, A1, A0, B35, B34, B33, B32, B31, B30, B29, B28, B27, B26, B25, B24
+, B23, B22, B21, B20, B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3
+, B2, B1, B0, C53, C52, C51, C50, C49, C48, C47, C46, C45, C44, C43, C42, C41, C40, C39, C38, C37, C36
+, C35, C34, C33, C32, C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17, C16, C15
+, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, CFB53, CFB52, CFB51, CFB50, CFB49, CFB48
+, CFB47, CFB46, CFB45, CFB44, CFB43, CFB42, CFB41, CFB40, CFB39, CFB38, CFB37, CFB36, CFB35, CFB34, CFB33, CFB32, CFB31, CFB30, CFB29, CFB28, CFB27
+, CFB26, CFB25, CFB24, CFB23, CFB22, CFB21, CFB20, CFB19, CFB18, CFB17, CFB16, CFB15, CFB14, CFB13, CFB12, CFB11, CFB10, CFB9, CFB8, CFB7, CFB6
+, CFB5, CFB4, CFB3, CFB2, CFB1, CFB0, MA35, MA34, MA33, MA32, MA31, MA30, MA29, MA28, MA27, MA26, MA25, MA24, MA23, MA22, MA21
+, MA20, MA19, MA18, MA17, MA16, MA15, MA14, MA13, MA12, MA11, MA10, MA9, MA8, MA7, MA6, MA5, MA4, MA3, MA2, MA1, MA0
+, MB35, MB34, MB33, MB32, MB31, MB30, MB29, MB28, MB27, MB26, MB25, MB24, MB23, MB22, MB21, MB20, MB19, MB18, MB17, MB16, MB15
+, MB14, MB13, MB12, MB11, MB10, MB9, MB8, MB7, MB6, MB5, MB4, MB3, MB2, MB1, MB0, CIN53, CIN52, CIN51, CIN50, CIN49, CIN48
+, CIN47, CIN46, CIN45, CIN44, CIN43, CIN42, CIN41, CIN40, CIN39, CIN38, CIN37, CIN36, CIN35, CIN34, CIN33, CIN32, CIN31, CIN30, CIN29, CIN28, CIN27
+, CIN26, CIN25, CIN24, CIN23, CIN22, CIN21, CIN20, CIN19, CIN18, CIN17, CIN16, CIN15, CIN14, CIN13, CIN12, CIN11, CIN10, CIN9, CIN8, CIN7, CIN6
+, CIN5, CIN4, CIN3, CIN2, CIN1, CIN0, OP10, OP9, OP8, OP7, OP6, OP5, OP4, OP3, OP2, OP1, OP0, R53, R52, R51, R50
+, R49, R48, R47, R46, R45, R44, R43, R42, R41, R40, R39, R38, R37, R36, R35, R34, R33, R32, R31, R30, R29
+, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R12, R11, R10, R9, R8
+, R7, R6, R5, R4, R3, R2, R1, R0, CO53, CO52, CO51, CO50, CO49, CO48, CO47, CO46, CO45, CO44, CO43, CO42, CO41
+, CO40, CO39, CO38, CO37, CO36, CO35, CO34, CO33, CO32, CO31, CO30, CO29, CO28, CO27, CO26, CO25, CO24, CO23, CO22, CO21, CO20
+, CO19, CO18, CO17, CO16, CO15, CO14, CO13, CO12, CO11, CO10, CO9, CO8, CO7, CO6, CO5, CO4, CO3, CO2, CO1, CO0, EQZ
+, EQZM, EQOM, EQPAT, EQPATB, OVER, UNDER, OVERUNDER, SIGNEDR);
     parameter REG_INPUTC0_CLK = "NONE";
     parameter REG_INPUTC0_CE = "CE0";
     parameter REG_INPUTC0_RST = "RST0";
@@ -970,7 +1007,7 @@ module ALU54B (...);
 endmodule
 
 (* blackbox *)
-module CLKDIVF (...);
+module CLKDIVF(CLKI, RST, ALIGNWD, CDIVX);
     parameter GSR = "DISABLED";
     parameter DIV = "2.0";
     input CLKI;
@@ -980,7 +1017,7 @@ module CLKDIVF (...);
 endmodule
 
 (* blackbox *)
-module PCSCLKDIV (...);
+module PCSCLKDIV(CLKI, RST, SEL2, SEL1, SEL0, CDIV1, CDIVX);
     parameter GSR = "DISABLED";
     input CLKI;
     input RST;
@@ -992,7 +1029,7 @@ module PCSCLKDIV (...);
 endmodule
 
 (* blackbox *)
-module DCSC (...);
+module DCSC(CLK1, CLK0, SEL1, SEL0, MODESEL, DCSOUT);
     parameter DCSMODE = "POS";
     input CLK1;
     input CLK0;
@@ -1003,21 +1040,21 @@ module DCSC (...);
 endmodule
 
 (* blackbox *)
-module DCCA (...);
+module DCCA(CLKI, CE, CLKO);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
 (* blackbox *)
-module ECLKSYNCB (...);
+module ECLKSYNCB(ECLKI, STOP, ECLKO);
     input ECLKI;
     input STOP;
     output ECLKO;
 endmodule
 
 (* blackbox *)
-module ECLKBRIDGECS (...);
+module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -1025,7 +1062,7 @@ module ECLKBRIDGECS (...);
 endmodule
 
 (* blackbox *)
-module DELAYF (...);
+module DELAYF(A, LOADN, MOVE, DIRECTION, Z, CFLAG);
     parameter DEL_MODE = "USER_DEFINED";
     parameter DEL_VALUE = 0;
     input A;
@@ -1037,7 +1074,7 @@ module DELAYF (...);
 endmodule
 
 (* blackbox *)
-module DELAYG (...);
+module DELAYG(A, Z);
     parameter DEL_MODE = "USER_DEFINED";
     parameter DEL_VALUE = 0;
     input A;
@@ -1045,13 +1082,14 @@ module DELAYG (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module USRMCLK (...);
+module USRMCLK(USRMCLKI, USRMCLKTS);
     input USRMCLKI;
     input USRMCLKTS;
 endmodule
 
 (* blackbox *)
-module DQSBUFM (...);
+module DQSBUFM(DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, ECLK, SCLK, RST, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, PAUSE, RDLOADN, RDMOVE
+, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID, BURSTDET, RDCFLAG, WRCFLAG);
     parameter DQS_LI_DEL_VAL = 4;
     parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
     parameter DQS_LO_DEL_VAL = 0;
@@ -1098,7 +1136,7 @@ module DQSBUFM (...);
 endmodule
 
 (* blackbox *)
-module DDRDLLA (...);
+module DDRDLLA(CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0);
     parameter FORCE_MAX_DELAY = "NO";
     parameter GSR = "ENABLED";
     input CLK;
@@ -1118,7 +1156,7 @@ module DDRDLLA (...);
 endmodule
 
 (* blackbox *)
-module DLLDELD (...);
+module DLLDELD(A, DDRDEL, LOADN, MOVE, DIRECTION, Z, CFLAG);
     input A;
     input DDRDEL;
     input LOADN;
@@ -1129,7 +1167,7 @@ module DLLDELD (...);
 endmodule
 
 (* blackbox *)
-module IDDRX1F (...);
+module IDDRX1F(D, SCLK, RST, Q0, Q1);
     parameter GSR = "ENABLED";
     input D;
     input SCLK;
@@ -1139,7 +1177,7 @@ module IDDRX1F (...);
 endmodule
 
 (* blackbox *)
-module IDDRX2F (...);
+module IDDRX2F(D, SCLK, ECLK, RST, ALIGNWD, Q3, Q2, Q1, Q0);
     parameter GSR = "ENABLED";
     input D;
     input SCLK;
@@ -1153,7 +1191,7 @@ module IDDRX2F (...);
 endmodule
 
 (* blackbox *)
-module IDDR71B (...);
+module IDDR71B(D, SCLK, ECLK, RST, ALIGNWD, Q6, Q5, Q4, Q3, Q2, Q1, Q0);
     parameter GSR = "ENABLED";
     input D;
     input SCLK;
@@ -1170,7 +1208,7 @@ module IDDR71B (...);
 endmodule
 
 (* blackbox *)
-module IDDRX2DQA (...);
+module IDDRX2DQA(SCLK, ECLK, DQSR90, D, RST, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, Q3, Q2, Q1, Q0, QWL);
     parameter GSR = "ENABLED";
     input SCLK;
     input ECLK;
@@ -1191,7 +1229,7 @@ module IDDRX2DQA (...);
 endmodule
 
 (* blackbox *)
-module ODDRX1F (...);
+module ODDRX1F(SCLK, RST, D0, D1, Q);
     parameter GSR = "ENABLED";
     input SCLK;
     input RST;
@@ -1201,7 +1239,7 @@ module ODDRX1F (...);
 endmodule
 
 (* blackbox *)
-module ODDRX2F (...);
+module ODDRX2F(SCLK, ECLK, RST, D3, D2, D1, D0, Q);
     parameter GSR = "ENABLED";
     input SCLK;
     input ECLK;
@@ -1214,7 +1252,7 @@ module ODDRX2F (...);
 endmodule
 
 (* blackbox *)
-module ODDR71B (...);
+module ODDR71B(SCLK, ECLK, RST, D6, D5, D4, D3, D2, D1, D0, Q);
     parameter GSR = "ENABLED";
     input SCLK;
     input ECLK;
@@ -1230,7 +1268,7 @@ module ODDR71B (...);
 endmodule
 
 (* blackbox *)
-module OSHX2A (...);
+module OSHX2A(D1, D0, SCLK, ECLK, RST, Q);
     parameter GSR = "ENABLED";
     input D1;
     input D0;
@@ -1241,7 +1279,7 @@ module OSHX2A (...);
 endmodule
 
 (* blackbox *)
-module TSHX2DQA (...);
+module TSHX2DQA(T1, T0, SCLK, ECLK, DQSW270, RST, Q);
     parameter GSR = "ENABLED";
     parameter REGSET = "SET";
     input T1;
@@ -1254,7 +1292,7 @@ module TSHX2DQA (...);
 endmodule
 
 (* blackbox *)
-module TSHX2DQSA (...);
+module TSHX2DQSA(T1, T0, SCLK, ECLK, DQSW, RST, Q);
     parameter GSR = "ENABLED";
     parameter REGSET = "SET";
     input T1;
@@ -1267,7 +1305,7 @@ module TSHX2DQSA (...);
 endmodule
 
 (* blackbox *)
-module ODDRX2DQA (...);
+module ODDRX2DQA(D3, D2, D1, D0, DQSW270, SCLK, ECLK, RST, Q);
     parameter GSR = "ENABLED";
     input D3;
     input D2;
@@ -1281,7 +1319,7 @@ module ODDRX2DQA (...);
 endmodule
 
 (* blackbox *)
-module ODDRX2DQSB (...);
+module ODDRX2DQSB(D3, D2, D1, D0, SCLK, ECLK, DQSW, RST, Q);
     parameter GSR = "ENABLED";
     input D3;
     input D2;
@@ -1295,7 +1333,8 @@ module ODDRX2DQSB (...);
 endmodule
 
 (* blackbox *)
-module EHXPLLL (...);
+module EHXPLLL(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, STDBY, PLLWAKESYNC, RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK
+, CLKINTFB);
     parameter CLKI_DIV = 1;
     parameter CLKFB_DIV = 1;
     parameter CLKOP_DIV = 8;
@@ -1357,7 +1396,7 @@ module EHXPLLL (...);
 endmodule
 
 (* blackbox *)
-module DTR (...);
+module DTR(STARTPULSE, DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0);
     parameter DTR_TEMP = 25;
     input STARTPULSE;
     output DTROUT7;
@@ -1371,13 +1410,13 @@ module DTR (...);
 endmodule
 
 (* blackbox *)
-module OSCG (...);
+module OSCG(OSC);
     parameter DIV = 128;
     output OSC;
 endmodule
 
 (* blackbox *)
-module EXTREFB (...);
+module EXTREFB(REFCLKP, REFCLKN, REFCLKO);
     parameter REFCK_PWDNB = "DONTCARE";
     parameter REFCK_RTERM = "DONTCARE";
     parameter REFCK_DCBIAS_EN = "DONTCARE";
@@ -1389,7 +1428,7 @@ module EXTREFB (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module JTAGG (...);
+module JTAGG(TCK, TMS, TDI, JTDO2, JTDO1, TDO, JTDI, JTCK, JRTI2, JRTI1, JSHIFT, JUPDATE, JRSTN, JCE2, JCE1);
     parameter ER1 = "ENABLED";
     parameter ER2 = "ENABLED";
     (* iopad_external_pin *)
@@ -1414,7 +1453,20 @@ module JTAGG (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module DCUA (...);
+module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2
+, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, CH0_FF_TX_D_12, CH1_FF_TX_D_12
+, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23
+, CH1_FF_TX_D_23, CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX
+, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB
+, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, CH0_SCIEN, CH1_SCIEN
+, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7
+, D_SCAN_MODE, D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND
+, D_TXPLL_LOL_TO_ND, CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3
+, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, CH0_FF_RX_D_14
+, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE
+, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE
+, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2
+, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, D_REFCLKI, D_FFS_PLOL);
     parameter D_MACROPDB = "DONTCARE";
     parameter D_IB_PWDNB = "DONTCARE";
     parameter D_XGE_MODE = "DONTCARE";

techlibs/lattice/cells_bb_xo2.v

@@ -1,18 +1,21 @@
 // Created by cells_xtra.py from Lattice models
 
 (* blackbox *) (* keep *)
-module GSR (...);
+module GSR(GSR);
     input GSR;
 endmodule
 
 (* blackbox *) (* keep *)
-module SGSR (...);
+module SGSR(GSR, CLK);
     input GSR;
     input CLK;
 endmodule
 
 (* blackbox *)
-module DP8KC (...);
+module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1
+, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10
+, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6
+, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0);
     parameter DATA_WIDTH_A = 9;
     parameter DATA_WIDTH_B = 9;
     parameter REGMODE_A = "NOREG";
@@ -138,7 +141,10 @@ module DP8KC (...);
 endmodule
 
 (* blackbox *)
-module PDPW8KC (...);
+module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6
+, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
+, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9
+, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter DATA_WIDTH_W = 18;
     parameter DATA_WIDTH_R = 9;
     parameter REGMODE = "NOREG";
@@ -255,7 +261,8 @@ module PDPW8KC (...);
 endmodule
 
 (* blackbox *)
-module SP8KC (...);
+module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1
+, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter DATA_WIDTH = 9;
     parameter REGMODE = "NOREG";
     parameter CSDECODE = "0b000";
@@ -338,7 +345,9 @@ module SP8KC (...);
 endmodule
 
 (* blackbox *)
-module FIFO8KB (...);
+module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0
+, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10
+, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF);
     parameter DATA_WIDTH_W = 18;
     parameter DATA_WIDTH_R = 18;
     parameter REGMODE = "NOREG";
@@ -409,7 +418,7 @@ module FIFO8KB (...);
 endmodule
 
 (* blackbox *)
-module CLKDIVC (...);
+module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX);
     parameter GSR = "DISABLED";
     parameter DIV = "2.0";
     input RST;
@@ -420,7 +429,7 @@ module CLKDIVC (...);
 endmodule
 
 (* blackbox *)
-module DCMA (...);
+module DCMA(CLK0, CLK1, SEL, DCMOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -428,14 +437,14 @@ module DCMA (...);
 endmodule
 
 (* blackbox *)
-module ECLKSYNCA (...);
+module ECLKSYNCA(ECLKI, STOP, ECLKO);
     input ECLKI;
     input STOP;
     output ECLKO;
 endmodule
 
 (* blackbox *)
-module ECLKBRIDGECS (...);
+module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -443,19 +452,21 @@ module ECLKBRIDGECS (...);
 endmodule
 
 (* blackbox *)
-module DCCA (...);
+module DCCA(CLKI, CE, CLKO);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
 (* blackbox *) (* keep *)
-module START (...);
+module START(STARTCLK);
     input STARTCLK;
 endmodule
 
 (* blackbox *)
-module EHXPLLJ (...);
+module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE
+, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7
+, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB);
     parameter CLKI_DIV = 1;
     parameter CLKFB_DIV = 1;
     parameter CLKOP_DIV = 8;
@@ -557,7 +568,7 @@ module EHXPLLJ (...);
 endmodule
 
 (* blackbox *)
-module OSCH (...);
+module OSCH(STDBY, OSC, SEDSTDBY);
     parameter NOM_FREQ = "2.08";
     input STDBY;
     output OSC;
@@ -565,7 +576,7 @@ module OSCH (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module TSALL (...);
+module TSALL(TSALL);
     input TSALL;
 endmodule
 

techlibs/lattice/cells_bb_xo3.v

@@ -1,18 +1,21 @@
 // Created by cells_xtra.py from Lattice models
 
 (* blackbox *) (* keep *)
-module GSR (...);
+module GSR(GSR);
     input GSR;
 endmodule
 
 (* blackbox *) (* keep *)
-module SGSR (...);
+module SGSR(GSR, CLK);
     input GSR;
     input CLK;
 endmodule
 
 (* blackbox *)
-module DP8KC (...);
+module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1
+, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10
+, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6
+, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0);
     parameter DATA_WIDTH_A = 9;
     parameter DATA_WIDTH_B = 9;
     parameter REGMODE_A = "NOREG";
@@ -138,7 +141,10 @@ module DP8KC (...);
 endmodule
 
 (* blackbox *)
-module PDPW8KC (...);
+module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6
+, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
+, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9
+, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter DATA_WIDTH_W = 18;
     parameter DATA_WIDTH_R = 9;
     parameter REGMODE = "NOREG";
@@ -255,7 +261,8 @@ module PDPW8KC (...);
 endmodule
 
 (* blackbox *)
-module SP8KC (...);
+module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1
+, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter DATA_WIDTH = 9;
     parameter REGMODE = "NOREG";
     parameter CSDECODE = "0b000";
@@ -338,7 +345,9 @@ module SP8KC (...);
 endmodule
 
 (* blackbox *)
-module FIFO8KB (...);
+module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0
+, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10
+, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF);
     parameter DATA_WIDTH_W = 18;
     parameter DATA_WIDTH_R = 18;
     parameter REGMODE = "NOREG";
@@ -409,7 +418,7 @@ module FIFO8KB (...);
 endmodule
 
 (* blackbox *)
-module CLKDIVC (...);
+module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX);
     parameter GSR = "DISABLED";
     parameter DIV = "2.0";
     input RST;
@@ -420,7 +429,7 @@ module CLKDIVC (...);
 endmodule
 
 (* blackbox *)
-module DCMA (...);
+module DCMA(CLK0, CLK1, SEL, DCMOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -428,14 +437,14 @@ module DCMA (...);
 endmodule
 
 (* blackbox *)
-module ECLKSYNCA (...);
+module ECLKSYNCA(ECLKI, STOP, ECLKO);
     input ECLKI;
     input STOP;
     output ECLKO;
 endmodule
 
 (* blackbox *)
-module ECLKBRIDGECS (...);
+module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -443,19 +452,21 @@ module ECLKBRIDGECS (...);
 endmodule
 
 (* blackbox *)
-module DCCA (...);
+module DCCA(CLKI, CE, CLKO);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
 (* blackbox *) (* keep *)
-module START (...);
+module START(STARTCLK);
     input STARTCLK;
 endmodule
 
 (* blackbox *)
-module EHXPLLJ (...);
+module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE
+, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7
+, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB);
     parameter CLKI_DIV = 1;
     parameter CLKFB_DIV = 1;
     parameter CLKOP_DIV = 8;
@@ -557,7 +568,7 @@ module EHXPLLJ (...);
 endmodule
 
 (* blackbox *)
-module OSCH (...);
+module OSCH(STDBY, OSC, SEDSTDBY);
     parameter NOM_FREQ = "2.08";
     input STDBY;
     output OSC;
@@ -565,7 +576,7 @@ module OSCH (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module TSALL (...);
+module TSALL(TSALL);
     input TSALL;
 endmodule
 

techlibs/lattice/cells_bb_xo3d.v

@@ -1,18 +1,21 @@
 // Created by cells_xtra.py from Lattice models
 
 (* blackbox *) (* keep *)
-module GSR (...);
+module GSR(GSR);
     input GSR;
 endmodule
 
 (* blackbox *) (* keep *)
-module SGSR (...);
+module SGSR(GSR, CLK);
     input GSR;
     input CLK;
 endmodule
 
 (* blackbox *)
-module DP8KC (...);
+module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1
+, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10
+, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6
+, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0);
     parameter DATA_WIDTH_A = 9;
     parameter DATA_WIDTH_B = 9;
     parameter REGMODE_A = "NOREG";
@@ -138,7 +141,10 @@ module DP8KC (...);
 endmodule
 
 (* blackbox *)
-module PDPW8KC (...);
+module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6
+, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
+, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9
+, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter DATA_WIDTH_W = 18;
     parameter DATA_WIDTH_R = 9;
     parameter REGMODE = "NOREG";
@@ -255,7 +261,8 @@ module PDPW8KC (...);
 endmodule
 
 (* blackbox *)
-module SP8KC (...);
+module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1
+, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
     parameter DATA_WIDTH = 9;
     parameter REGMODE = "NOREG";
     parameter CSDECODE = "0b000";
@@ -338,7 +345,9 @@ module SP8KC (...);
 endmodule
 
 (* blackbox *)
-module FIFO8KB (...);
+module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0
+, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10
+, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF);
     parameter DATA_WIDTH_W = 18;
     parameter DATA_WIDTH_R = 18;
     parameter REGMODE = "NOREG";
@@ -409,7 +418,7 @@ module FIFO8KB (...);
 endmodule
 
 (* blackbox *)
-module CLKDIVC (...);
+module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX);
     parameter GSR = "DISABLED";
     parameter DIV = "2.0";
     input RST;
@@ -420,7 +429,7 @@ module CLKDIVC (...);
 endmodule
 
 (* blackbox *)
-module DCMA (...);
+module DCMA(CLK0, CLK1, SEL, DCMOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -428,14 +437,14 @@ module DCMA (...);
 endmodule
 
 (* blackbox *)
-module ECLKSYNCA (...);
+module ECLKSYNCA(ECLKI, STOP, ECLKO);
     input ECLKI;
     input STOP;
     output ECLKO;
 endmodule
 
 (* blackbox *)
-module ECLKBRIDGECS (...);
+module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
     input CLK0;
     input CLK1;
     input SEL;
@@ -443,19 +452,21 @@ module ECLKBRIDGECS (...);
 endmodule
 
 (* blackbox *)
-module DCCA (...);
+module DCCA(CLKI, CE, CLKO);
     input CLKI;
     input CE;
     output CLKO;
 endmodule
 
 (* blackbox *) (* keep *)
-module START (...);
+module START(STARTCLK);
     input STARTCLK;
 endmodule
 
 (* blackbox *)
-module EHXPLLJ (...);
+module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE
+, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7
+, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB);
     parameter CLKI_DIV = 1;
     parameter CLKFB_DIV = 1;
     parameter CLKOP_DIV = 8;
@@ -557,7 +568,7 @@ module EHXPLLJ (...);
 endmodule
 
 (* blackbox *)
-module OSCJ (...);
+module OSCJ(STDBY, OSC, SEDSTDBY, OSCESB);
     parameter NOM_FREQ = "2.08";
     input STDBY;
     output OSC;
@@ -566,7 +577,7 @@ module OSCJ (...);
 endmodule
 
 (* blackbox *) (* keep *)
-module TSALL (...);
+module TSALL(TSALL);
     input TSALL;
 endmodule
 

techlibs/xilinx/synth_xilinx.cc

@@ -386,6 +386,8 @@ struct SynthXilinxPass : public ScriptPass
 				run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
 				run("clean", "      (skip if '-nosrl' and '-widemux=0')");
 			}
+
+			run("sort");
 		}
 
 		if (check_label("map_dsp", "(skip if '-nodsp')")) {

tests/blif/.gitignore

@@ -0,0 +1 @@
+/*.out

tests/blif/gatesi.blif

@@ -0,0 +1,480 @@
+# Generated by Yosys 0.60+88 (git sha1 69b604104, g++ 15.2.1 -fPIC -O3)
+
+.model test
+.inputs clk in_a_var[0] in_a_var[1] in_a_var[2] in_a_var[3] in_a_var[4] in_a_var[5] in_a_var[6] in_a_var[7] in_b_var[0] in_b_var[1] in_b_var[2] in_b_var[3] in_b_var[4] in_b_var[5] in_b_var[6] in_b_var[7]
+.outputs out_var[0] out_var[1] out_var[2] out_var[3] out_var[4] out_var[5] out_var[6] out_var[7]
+.gate ORNOT A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n57
+.gate ORNOT A=in_a_var[0] B=:1.test_1[0] Y=$abc$2385$new_n58
+.gate XNOR A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n59
+.gate NAND A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$new_n60
+.gate XOR A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0]
+.gate NAND A=$abc$2385$new_n57 B=$abc$2385$new_n60 Y=$abc$2385$new_n62
+.gate NOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n63
+.gate AND A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n64
+.gate XOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n65
+.gate NOT A=$abc$2385$new_n65 Y=$abc$2385$new_n66
+.gate AND A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n67
+.gate AND A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n68
+.gate AND A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n69
+.gate AND A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n70
+.gate AND A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n71
+.gate XNOR A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n72
+.gate NOT A=$abc$2385$new_n72 Y=$abc$2385$new_n73
+.gate AND A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n74
+.gate XNOR A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n75
+.gate ANDNOT A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n76
+.gate XNOR A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n77
+.gate NOR A=:1.test_1[3] B=:1.test_1[4] Y=$abc$2385$new_n78
+.gate AND A=$abc$2385$new_n63 B=$abc$2385$new_n78 Y=$abc$2385$new_n79
+.gate ANDNOT A=$abc$2385$new_n79 B=:1.test_1[2] Y=$abc$2385$new_n80
+.gate AND A=$abc$2385$new_n77 B=$abc$2385$new_n80 Y=$abc$2385$new_n81
+.gate NAND A=$abc$2385$new_n75 B=$abc$2385$new_n81 Y=$abc$2385$new_n82
+.gate OR A=$abc$2385$new_n73 B=$abc$2385$new_n82 Y=$abc$2385$new_n83
+.gate AND A=$abc$2385$new_n66 B=$abc$2385$new_n83 Y=$abc$2385$new_n84
+.gate ORNOT A=$abc$2385$new_n84 B=in_a_var[1] Y=$abc$2385$new_n85
+.gate XNOR A=in_a_var[1] B=$abc$2385$new_n84 Y=$abc$2385$new_n86
+.gate NAND A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n87
+.gate XNOR A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n88
+.gate ANDNOT A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$new_n89
+.gate AND A=$abc$2385$new_n85 B=$abc$2385$new_n87 Y=$abc$2385$new_n90
+.gate XNOR A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n91
+.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n91 Y=$abc$2385$new_n92
+.gate ORNOT A=$abc$2385$new_n92 B=in_a_var[2] Y=$abc$2385$new_n93
+.gate XNOR A=in_a_var[2] B=$abc$2385$new_n92 Y=$abc$2385$new_n94
+.gate NAND A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n95
+.gate XNOR A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n96
+.gate OR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n97
+.gate XOR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n98
+.gate NAND A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$new_n99
+.gate XOR A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2]
+.gate NAND A=$abc$2385$new_n97 B=$abc$2385$new_n99 Y=$abc$2385$new_n101
+.gate AND A=$abc$2385$new_n93 B=$abc$2385$new_n95 Y=$abc$2385$new_n102
+.gate XNOR A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n103
+.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n103 Y=$abc$2385$new_n104
+.gate ORNOT A=$abc$2385$new_n104 B=in_a_var[3] Y=$abc$2385$new_n105
+.gate XNOR A=in_a_var[3] B=$abc$2385$new_n104 Y=$abc$2385$new_n106
+.gate NAND A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n107
+.gate XNOR A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n108
+.gate OR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n109
+.gate XOR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n110
+.gate NAND A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$new_n111
+.gate XOR A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3]
+.gate NAND A=$abc$2385$new_n109 B=$abc$2385$new_n111 Y=$abc$2385$new_n113
+.gate AND A=$abc$2385$new_n105 B=$abc$2385$new_n107 Y=$abc$2385$new_n114
+.gate XNOR A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n115
+.gate AND A=$abc$2385$new_n83 B=$abc$2385$new_n115 Y=$abc$2385$new_n116
+.gate ORNOT A=$abc$2385$new_n116 B=in_a_var[4] Y=$abc$2385$new_n117
+.gate XNOR A=in_a_var[4] B=$abc$2385$new_n116 Y=$abc$2385$new_n118
+.gate NAND A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n119
+.gate XNOR A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n120
+.gate OR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n121
+.gate XOR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n122
+.gate NAND A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$new_n123
+.gate XOR A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4]
+.gate AND A=$abc$2385$new_n121 B=$abc$2385$new_n123 Y=$abc$2385$new_n125
+.gate AND A=$abc$2385$new_n117 B=$abc$2385$new_n119 Y=$abc$2385$new_n126
+.gate AND A=$abc$2385$new_n77 B=$abc$2385$new_n83 Y=$abc$2385$new_n127
+.gate ORNOT A=$abc$2385$new_n127 B=in_a_var[5] Y=$abc$2385$new_n128
+.gate XNOR A=in_a_var[5] B=$abc$2385$new_n127 Y=$abc$2385$new_n129
+.gate NAND A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n130
+.gate XNOR A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n131
+.gate OR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n132
+.gate NAND A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n133
+.gate XOR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n134
+.gate XNOR A=$abc$2385$new_n125 B=$abc$2385$new_n134 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5]
+.gate AND A=$abc$2385$new_n128 B=$abc$2385$new_n130 Y=$abc$2385$new_n136
+.gate AND A=$abc$2385$new_n72 B=$abc$2385$new_n82 Y=$abc$2385$new_n137
+.gate ORNOT A=$abc$2385$new_n137 B=in_a_var[6] Y=$abc$2385$new_n138
+.gate XNOR A=in_a_var[6] B=$abc$2385$new_n137 Y=$abc$2385$new_n139
+.gate NAND A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n140
+.gate XNOR A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n141
+.gate OR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n142
+.gate XOR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n143
+.gate NAND A=$abc$2385$new_n125 B=$abc$2385$new_n132 Y=$abc$2385$new_n144
+.gate AND A=$abc$2385$new_n133 B=$abc$2385$new_n144 Y=$abc$2385$new_n145
+.gate NAND A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$new_n146
+.gate XOR A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6]
+.gate AND A=$abc$2385$new_n142 B=$abc$2385$new_n146 Y=$abc$2385$new_n148
+.gate AND A=$abc$2385$new_n138 B=$abc$2385$new_n140 Y=$abc$2385$new_n149
+.gate AND A=$abc$2385$new_n75 B=$abc$2385$new_n83 Y=$abc$2385$new_n150
+.gate NOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n151
+.gate XOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n152
+.gate XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n152 Y=$abc$2385$new_n153
+.gate XNOR A=$abc$2385$new_n149 B=$abc$2385$new_n153 Y=$abc$2385$new_n154
+.gate XNOR A=$abc$2385$new_n148 B=$abc$2385$new_n154 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7]
+.gate XNOR A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$auto$maccmap.cc:240:synth$253.P[1]
+.gate NAND A=:1.test_1[0] B=:1.test_2[0] Y=$abc$2385$new_n157
+.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n91 Y=$abc$2385$new_n158
+.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n64 Y=$abc$2385$new_n159
+.gate AND A=:1.test_2[1] B=$abc$2385$new_n65 Y=$abc$2385$new_n160
+.gate ORNOT A=$abc$2385$new_n160 B=:1.test_1[0] Y=$abc$2385$new_n161
+.gate AND A=:1.test_2[2] B=$abc$2385$new_n161 Y=$abc$2385$new_n162
+.gate ANDNOT A=:1.test_1[1] B=:1.test_1[0] Y=$abc$2385$new_n163
+.gate ANDNOT A=:1.test_2[2] B=:1.test_1[0] Y=$abc$2385$new_n164
+.gate XNOR A=$abc$2385$new_n160 B=$abc$2385$new_n164 Y=$abc$2385$new_n165
+.gate MUX A=$abc$2385$new_n160 B=$abc$2385$new_n165 S=:1.test_2[2] Y=$abc$2385$new_n166
+.gate ORNOT A=:1.test_2[0] B=:1.test_1[0] Y=$abc$2385$new_n167
+.gate AND A=$abc$2385$new_n159 B=$abc$2385$new_n167 Y=$abc$2385$new_n168
+.gate AND A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n169
+.gate XOR A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n170
+.gate AND A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n171
+.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n103 Y=$abc$2385$new_n172
+.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n91 Y=$abc$2385$new_n173
+.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n103 Y=$abc$2385$new_n174
+.gate AND A=$abc$2385$new_n158 B=$abc$2385$new_n174 Y=$abc$2385$new_n175
+.gate XOR A=$abc$2385$new_n172 B=$abc$2385$new_n173 Y=$abc$2385$new_n176
+.gate NAND A=:1.test_2[2] B=$abc$2385$new_n65 Y=$abc$2385$new_n177
+.gate AND A=:1.test_1[0] B=:1.test_2[3] Y=$abc$2385$new_n178
+.gate NAND A=:1.test_1[0] B=$abc$2385$new_n177 Y=$abc$2385$new_n179
+.gate XNOR A=$abc$2385$new_n177 B=$abc$2385$new_n178 Y=$abc$2385$new_n180
+.gate NAND A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n181
+.gate XOR A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n182
+.gate NAND A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n183
+.gate XOR A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n184
+.gate NAND A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n185
+.gate XOR A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n186
+.gate NAND A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n187
+.gate NAND A=$abc$2385$new_n185 B=$abc$2385$new_n187 Y=$abc$2385$new_n188
+.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n115 Y=$abc$2385$new_n189
+.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n115 Y=$abc$2385$new_n190
+.gate NAND A=$abc$2385$new_n172 B=$abc$2385$new_n190 Y=$abc$2385$new_n191
+.gate XOR A=$abc$2385$new_n174 B=$abc$2385$new_n189 Y=$abc$2385$new_n192
+.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n91 Y=$abc$2385$new_n193
+.gate NAND A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n194
+.gate XOR A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n195
+.gate AND A=:1.test_2[3] B=$abc$2385$new_n179 Y=$abc$2385$new_n196
+.gate NAND A=:1.test_2[3] B=$abc$2385$new_n65 Y=$abc$2385$new_n197
+.gate NAND A=:1.test_1[0] B=$abc$2385$new_n197 Y=$abc$2385$new_n198
+.gate AND A=:1.test_2[4] B=$abc$2385$new_n198 Y=$abc$2385$new_n199
+.gate NAND A=:1.test_2[3] B=$abc$2385$new_n163 Y=$abc$2385$new_n200
+.gate NAND A=$abc$2385$new_n199 B=$abc$2385$new_n200 Y=$abc$2385$new_n201
+.gate ORNOT A=:1.test_2[4] B=$abc$2385$new_n197 Y=$abc$2385$new_n202
+.gate AND A=$abc$2385$new_n201 B=$abc$2385$new_n202 Y=$abc$2385$new_n203
+.gate NAND A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n204
+.gate XOR A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n205
+.gate NAND A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n206
+.gate XOR A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n207
+.gate AND A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n208
+.gate XOR A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n209
+.gate NAND A=$abc$2385$new_n181 B=$abc$2385$new_n183 Y=$abc$2385$new_n210
+.gate AND A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n211
+.gate XOR A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n212
+.gate AND A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n213
+.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n77 Y=$abc$2385$new_n214
+.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n91 Y=$abc$2385$new_n215
+.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n103 Y=$abc$2385$new_n216
+.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n115 Y=$abc$2385$new_n217
+.gate NAND A=$abc$2385$new_n174 B=$abc$2385$new_n217 Y=$abc$2385$new_n218
+.gate XOR A=$abc$2385$new_n190 B=$abc$2385$new_n216 Y=$abc$2385$new_n219
+.gate NAND A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n220
+.gate XOR A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n221
+.gate AND A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n222
+.gate XOR A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n223
+.gate NAND A=:1.test_2[4] B=$abc$2385$new_n65 Y=$abc$2385$new_n224
+.gate NAND A=:1.test_1[0] B=$abc$2385$new_n224 Y=$abc$2385$new_n225
+.gate AND A=:1.test_2[5] B=$abc$2385$new_n225 Y=$abc$2385$new_n226
+.gate NAND A=:1.test_2[4] B=$abc$2385$new_n163 Y=$abc$2385$new_n227
+.gate NAND A=$abc$2385$new_n226 B=$abc$2385$new_n227 Y=$abc$2385$new_n228
+.gate ORNOT A=:1.test_2[5] B=$abc$2385$new_n224 Y=$abc$2385$new_n229
+.gate AND A=$abc$2385$new_n228 B=$abc$2385$new_n229 Y=$abc$2385$new_n230
+.gate NAND A=$abc$2385$new_n191 B=$abc$2385$new_n194 Y=$abc$2385$new_n231
+.gate NAND A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n232
+.gate XOR A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n233
+.gate NAND A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n234
+.gate XOR A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n235
+.gate AND A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n236
+.gate XOR A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n237
+.gate NAND A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n238
+.gate XOR A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n239
+.gate NAND A=$abc$2385$new_n204 B=$abc$2385$new_n206 Y=$abc$2385$new_n240
+.gate NAND A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n241
+.gate XOR A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n242
+.gate AND A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n243
+.gate XOR A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n244
+.gate NAND A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n245
+.gate AND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n246
+.gate NAND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n247
+.gate XOR A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n248
+.gate AND A=$abc$2385$new_n246 B=$abc$2385$new_n248 Y=$abc$2385$new_n249
+.gate XOR A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n250
+.gate AND A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n251
+.gate XOR A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n252
+.gate AND A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n253
+.gate NAND A=$abc$2385$new_n244 B=$abc$2385$new_n253 Y=$abc$2385$new_n254
+.gate XNOR A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n255
+.gate NAND A=$abc$2385$new_n245 B=$abc$2385$new_n254 Y=$abc$2385$new_n256
+.gate NAND A=$abc$2385$new_n238 B=$abc$2385$new_n241 Y=$abc$2385$new_n257
+.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n72 Y=$abc$2385$new_n258
+.gate ORNOT A=$abc$2385$new_n77 B=:1.test_2[1] Y=$abc$2385$new_n259
+.gate ANDNOT A=:1.test_2[1] B=$abc$2385$new_n72 Y=$abc$2385$new_n260
+.gate NAND A=$abc$2385$new_n214 B=$abc$2385$new_n260 Y=$abc$2385$new_n261
+.gate XNOR A=$abc$2385$new_n258 B=$abc$2385$new_n259 Y=$abc$2385$new_n262
+.gate ANDNOT A=:1.test_2[4] B=$abc$2385$new_n91 Y=$abc$2385$new_n263
+.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n103 Y=$abc$2385$new_n264
+.gate ANDNOT A=:1.test_2[3] B=$abc$2385$new_n115 Y=$abc$2385$new_n265
+.gate NAND A=$abc$2385$new_n216 B=$abc$2385$new_n265 Y=$abc$2385$new_n266
+.gate XOR A=$abc$2385$new_n217 B=$abc$2385$new_n264 Y=$abc$2385$new_n267
+.gate NAND A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n268
+.gate XOR A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n269
+.gate AND A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n270
+.gate XOR A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n271
+.gate NAND A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n272
+.gate XOR A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n273
+.gate NAND A=:1.test_2[5] B=$abc$2385$new_n65 Y=$abc$2385$new_n274
+.gate NAND A=:1.test_1[0] B=$abc$2385$new_n274 Y=$abc$2385$new_n275
+.gate AND A=:1.test_2[6] B=$abc$2385$new_n275 Y=$abc$2385$new_n276
+.gate NAND A=:1.test_2[5] B=$abc$2385$new_n163 Y=$abc$2385$new_n277
+.gate NAND A=:1.test_2[6] B=$abc$2385$new_n65 Y=$abc$2385$new_n278
+.gate NAND A=$abc$2385$new_n276 B=$abc$2385$new_n277 Y=$abc$2385$new_n279
+.gate ORNOT A=:1.test_2[6] B=$abc$2385$new_n274 Y=$abc$2385$new_n280
+.gate AND A=$abc$2385$new_n279 B=$abc$2385$new_n280 Y=$abc$2385$new_n281
+.gate NAND A=$abc$2385$new_n218 B=$abc$2385$new_n220 Y=$abc$2385$new_n282
+.gate NAND A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n283
+.gate XOR A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n284
+.gate NAND A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n285
+.gate XOR A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n286
+.gate NAND A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n287
+.gate XOR A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n288
+.gate NAND A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n289
+.gate XOR A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n290
+.gate NAND A=$abc$2385$new_n232 B=$abc$2385$new_n234 Y=$abc$2385$new_n291
+.gate NAND A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n292
+.gate XOR A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n293
+.gate NAND A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n294
+.gate XOR A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n295
+.gate NAND A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n296
+.gate XOR A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n297
+.gate NAND A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n298
+.gate XNOR A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n299
+.gate NAND A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n300
+.gate OR A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n301
+.gate XOR A=$abc$2385$new_n253 B=$abc$2385$new_n255 Y=$abc$2385$new_n302
+.gate XNOR A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n303
+.gate XOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n304
+.gate XNOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n305
+.gate NAND A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n306
+.gate OR A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n307
+.gate XNOR A=$abc$2385$new_n247 B=$abc$2385$new_n248 Y=$abc$2385$new_n308
+.gate NAND A=:1.test_1[0] B=:1.test_2[1] Y=$abc$2385$new_n309
+.gate ANDNOT A=:1.test_2[0] B=$abc$2385$new_n64 Y=$abc$2385$new_n310
+.gate XNOR A=$abc$2385$new_n309 B=$abc$2385$new_n310 Y=$abc$2385$new_n311
+.gate NAND A=$abc$2385$new_n66 B=$abc$2385$new_n311 Y=$abc$2385$new_n312
+.gate OR A=:1.test_2[1] B=$abc$2385$new_n157 Y=$abc$2385$new_n313
+.gate NAND A=$abc$2385$new_n312 B=$abc$2385$new_n313 Y=$abc$2385$new_n314
+.gate OR A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n315
+.gate NAND A=$abc$2385$new_n91 B=$abc$2385$new_n315 Y=$abc$2385$new_n316
+.gate NAND A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n317
+.gate NAND A=$abc$2385$new_n316 B=$abc$2385$new_n317 Y=$abc$2385$new_n318
+.gate NAND A=$abc$2385$new_n307 B=$abc$2385$new_n318 Y=$abc$2385$new_n319
+.gate NAND A=$abc$2385$new_n247 B=$abc$2385$new_n311 Y=$abc$2385$new_n320
+.gate NAND A=$abc$2385$new_n306 B=$abc$2385$new_n319 Y=$abc$2385$new_n321
+.gate ORNOT A=$abc$2385$new_n115 B=$abc$2385$new_n303 Y=$abc$2385$new_n322
+.gate ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n115 Y=$abc$2385$new_n323
+.gate NAND A=$abc$2385$new_n321 B=$abc$2385$new_n322 Y=$abc$2385$new_n324
+.gate NAND A=$abc$2385$new_n323 B=$abc$2385$new_n324 Y=$abc$2385$new_n325
+.gate NAND A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n326
+.gate NAND A=$abc$2385$new_n302 B=$abc$2385$new_n326 Y=$abc$2385$new_n327
+.gate OR A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n328
+.gate AND A=$abc$2385$new_n327 B=$abc$2385$new_n328 Y=$abc$2385$new_n329
+.gate NAND A=$abc$2385$new_n300 B=$abc$2385$new_n329 Y=$abc$2385$new_n330
+.gate AND A=$abc$2385$new_n301 B=$abc$2385$new_n330 Y=$abc$2385$new_n331
+.gate NAND A=$abc$2385$new_n75 B=$abc$2385$new_n331 Y=$abc$2385$new_n332
+.gate OR A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n333
+.gate NAND A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n334
+.gate OR A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n335
+.gate AND A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n336
+.gate OR A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n337
+.gate ANDNOT A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n338
+.gate XNOR A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n339
+.gate NAND A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n340
+.gate XNOR A=in_b_var[3] B=$abc$2385$new_n304 Y=$abc$2385$new_n341
+.gate AND A=$abc$2385$new_n339 B=$abc$2385$new_n341 Y=$abc$2385$new_n342
+.gate NAND A=$abc$2385$new_n336 B=$abc$2385$new_n342 Y=$abc$2385$new_n343
+.gate NAND A=$abc$2385$new_n337 B=$abc$2385$new_n338 Y=$abc$2385$new_n344
+.gate AND A=$abc$2385$new_n340 B=$abc$2385$new_n344 Y=$abc$2385$new_n345
+.gate AND A=$abc$2385$new_n343 B=$abc$2385$new_n345 Y=$abc$2385$new_n346
+.gate AND A=in_b_var[0] B=$abc$2385$new_n157 Y=$abc$2385$new_n347
+.gate XOR A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n348
+.gate AND A=$abc$2385$new_n342 B=$abc$2385$new_n348 Y=$abc$2385$new_n349
+.gate NAND A=$abc$2385$new_n347 B=$abc$2385$new_n349 Y=$abc$2385$new_n350
+.gate NAND A=$abc$2385$new_n346 B=$abc$2385$new_n350 Y=$abc$2385$new_n351
+.gate NAND A=$abc$2385$new_n335 B=$abc$2385$new_n351 Y=$abc$2385$new_n352
+.gate NAND A=$abc$2385$new_n334 B=$abc$2385$new_n352 Y=$abc$2385$new_n353
+.gate NAND A=$abc$2385$new_n333 B=$abc$2385$new_n353 Y=$abc$2385$new_n354
+.gate NAND A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n355
+.gate NAND A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n356
+.gate AND A=$abc$2385$new_n355 B=$abc$2385$new_n356 Y=$abc$2385$new_n357
+.gate NAND A=$abc$2385$new_n354 B=$abc$2385$new_n357 Y=$abc$2385$new_n358
+.gate AND A=$abc$2385$new_n157 B=$abc$2385$new_n320 Y=$abc$2385$new_n359
+.gate ANDNOT A=$abc$2385$new_n359 B=$abc$2385$new_n308 Y=$abc$2385$new_n360
+.gate AND A=$abc$2385$new_n305 B=$abc$2385$new_n360 Y=$abc$2385$new_n361
+.gate AND A=$abc$2385$new_n303 B=$abc$2385$new_n361 Y=$abc$2385$new_n362
+.gate AND A=$abc$2385$new_n302 B=$abc$2385$new_n362 Y=$abc$2385$new_n363
+.gate NAND A=$abc$2385$new_n299 B=$abc$2385$new_n363 Y=$abc$2385$new_n364
+.gate AND A=$abc$2385$new_n296 B=$abc$2385$new_n298 Y=$abc$2385$new_n365
+.gate AND A=$abc$2385$new_n289 B=$abc$2385$new_n292 Y=$abc$2385$new_n366
+.gate OR A=:1.test_2[0] B=$abc$2385$new_n75 Y=$abc$2385$new_n367
+.gate AND A=$abc$2385$new_n261 B=$abc$2385$new_n367 Y=$abc$2385$new_n368
+.gate XNOR A=$abc$2385$new_n270 B=$abc$2385$new_n368 Y=$abc$2385$new_n369
+.gate XNOR A=$abc$2385$new_n276 B=$abc$2385$new_n369 Y=$abc$2385$new_n370
+.gate ANDNOT A=:1.test_2[2] B=$abc$2385$new_n77 Y=$abc$2385$new_n371
+.gate ANDNOT A=:1.test_2[5] B=$abc$2385$new_n91 Y=$abc$2385$new_n372
+.gate ANDNOT A=:1.test_2[4] B=$abc$2385$new_n103 Y=$abc$2385$new_n373
+.gate XNOR A=$abc$2385$new_n372 B=$abc$2385$new_n373 Y=$abc$2385$new_n374
+.gate XNOR A=$abc$2385$new_n371 B=$abc$2385$new_n374 Y=$abc$2385$new_n375
+.gate XOR A=$abc$2385$new_n260 B=$abc$2385$new_n265 Y=$abc$2385$new_n376
+.gate XNOR A=$abc$2385$new_n375 B=$abc$2385$new_n376 Y=$abc$2385$new_n377
+.gate NAND A=$abc$2385$new_n266 B=$abc$2385$new_n268 Y=$abc$2385$new_n378
+.gate ANDNOT A=:1.test_2[7] B=:1.test_1[0] Y=$abc$2385$new_n379
+.gate XNOR A=$abc$2385$new_n278 B=$abc$2385$new_n379 Y=$abc$2385$new_n380
+.gate XNOR A=$abc$2385$new_n75 B=$abc$2385$new_n380 Y=$abc$2385$new_n381
+.gate XNOR A=$abc$2385$new_n378 B=$abc$2385$new_n381 Y=$abc$2385$new_n382
+.gate XNOR A=$abc$2385$new_n377 B=$abc$2385$new_n382 Y=$abc$2385$new_n383
+.gate XNOR A=$abc$2385$new_n370 B=$abc$2385$new_n383 Y=$abc$2385$new_n384
+.gate NAND A=$abc$2385$new_n283 B=$abc$2385$new_n285 Y=$abc$2385$new_n385
+.gate AND A=$abc$2385$new_n272 B=$abc$2385$new_n287 Y=$abc$2385$new_n386
+.gate XNOR A=$abc$2385$new_n385 B=$abc$2385$new_n386 Y=$abc$2385$new_n387
+.gate XNOR A=$abc$2385$new_n384 B=$abc$2385$new_n387 Y=$abc$2385$new_n388
+.gate XNOR A=$abc$2385$new_n366 B=$abc$2385$new_n388 Y=$abc$2385$new_n389
+.gate XNOR A=:1.test_2[7] B=$abc$2385$new_n294 Y=$abc$2385$new_n390
+.gate XNOR A=$abc$2385$new_n389 B=$abc$2385$new_n390 Y=$abc$2385$new_n391
+.gate XNOR A=$abc$2385$new_n365 B=$abc$2385$new_n391 Y=$abc$2385$new_n392
+.gate OR A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n393
+.gate ORNOT A=in_b_var[6] B=in_a_var[6] Y=$abc$2385$new_n394
+.gate ORNOT A=in_a_var[5] B=in_b_var[5] Y=$abc$2385$new_n395
+.gate ORNOT A=in_b_var[5] B=in_a_var[5] Y=$abc$2385$new_n396
+.gate ORNOT A=in_b_var[4] B=in_a_var[4] Y=$abc$2385$new_n397
+.gate AND A=$abc$2385$new_n396 B=$abc$2385$new_n397 Y=$abc$2385$new_n398
+.gate ORNOT A=in_b_var[2] B=in_a_var[2] Y=$abc$2385$new_n399
+.gate ORNOT A=in_b_var[3] B=in_a_var[3] Y=$abc$2385$new_n400
+.gate NAND A=$abc$2385$new_n399 B=$abc$2385$new_n400 Y=$abc$2385$new_n401
+.gate ORNOT A=in_a_var[3] B=in_b_var[3] Y=$abc$2385$new_n402
+.gate NAND A=$abc$2385$new_n401 B=$abc$2385$new_n402 Y=$abc$2385$new_n403
+.gate ORNOT A=in_a_var[2] B=in_b_var[2] Y=$abc$2385$new_n404
+.gate NAND A=$abc$2385$new_n402 B=$abc$2385$new_n404 Y=$abc$2385$new_n405
+.gate NOR A=$abc$2385$new_n401 B=$abc$2385$new_n405 Y=$abc$2385$new_n406
+.gate ORNOT A=in_a_var[0] B=in_b_var[0] Y=$abc$2385$new_n407
+.gate ORNOT A=in_a_var[1] B=in_b_var[1] Y=$abc$2385$new_n408
+.gate NAND A=$abc$2385$new_n407 B=$abc$2385$new_n408 Y=$abc$2385$new_n409
+.gate ORNOT A=in_b_var[1] B=in_a_var[1] Y=$abc$2385$new_n410
+.gate NAND A=$abc$2385$new_n409 B=$abc$2385$new_n410 Y=$abc$2385$new_n411
+.gate NAND A=$abc$2385$new_n406 B=$abc$2385$new_n411 Y=$abc$2385$new_n412
+.gate NAND A=$abc$2385$new_n403 B=$abc$2385$new_n412 Y=$abc$2385$new_n413
+.gate ORNOT A=in_a_var[4] B=in_b_var[4] Y=$abc$2385$new_n414
+.gate NAND A=$abc$2385$new_n413 B=$abc$2385$new_n414 Y=$abc$2385$new_n415
+.gate NAND A=$abc$2385$new_n398 B=$abc$2385$new_n415 Y=$abc$2385$new_n416
+.gate NAND A=$abc$2385$new_n395 B=$abc$2385$new_n416 Y=$abc$2385$new_n417
+.gate NAND A=$abc$2385$new_n394 B=$abc$2385$new_n417 Y=$abc$2385$new_n418
+.gate NAND A=$abc$2385$new_n394 B=$abc$2385$new_n395 Y=$abc$2385$new_n419
+.gate NOR A=$abc$2385$new_n409 B=$abc$2385$new_n419 Y=$abc$2385$new_n420
+.gate AND A=$abc$2385$new_n398 B=$abc$2385$new_n420 Y=$abc$2385$new_n421
+.gate ORNOT A=in_b_var[0] B=in_a_var[0] Y=$abc$2385$new_n422
+.gate AND A=$abc$2385$new_n410 B=$abc$2385$new_n414 Y=$abc$2385$new_n423
+.gate AND A=$abc$2385$new_n422 B=$abc$2385$new_n423 Y=$abc$2385$new_n424
+.gate AND A=$abc$2385$new_n406 B=$abc$2385$new_n424 Y=$abc$2385$new_n425
+.gate NAND A=$abc$2385$new_n421 B=$abc$2385$new_n425 Y=$abc$2385$new_n426
+.gate ORNOT A=in_a_var[6] B=in_b_var[6] Y=$abc$2385$new_n427
+.gate AND A=$abc$2385$new_n151 B=$abc$2385$new_n427 Y=$abc$2385$new_n428
+.gate AND A=$abc$2385$new_n426 B=$abc$2385$new_n428 Y=$abc$2385$new_n429
+.gate AND A=$abc$2385$new_n418 B=$abc$2385$new_n429 Y=$abc$2385$new_n430
+.gate AND A=$abc$2385$new_n393 B=$abc$2385$new_n430 Y=$abc$2385$new_n431
+.gate AND A=$abc$2385$new_n392 B=$abc$2385$new_n431 Y=$abc$2385$new_n432
+.gate AND A=$abc$2385$new_n364 B=$abc$2385$new_n432 Y=$abc$2385$new_n433
+.gate AND A=$abc$2385$new_n358 B=$abc$2385$new_n433 Y=$abc$2385$new_n434
+.gate AND A=$abc$2385$new_n332 B=$abc$2385$new_n434 Y=$abc$2385$new_n435
+.gate AND A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n436
+.gate XNOR A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n437
+.gate ORNOT A=$abc$2385$new_n74 B=:1.test_1[0] Y=$abc$2385$new_n438
+.gate MUX A=:1.test_1[0] B=$abc$2385$new_n437 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[0]
+.gate ORNOT A=:1.test_1[1] B=$abc$2385$new_n83 Y=$abc$2385$new_n440
+.gate XNOR A=$abc$2385$new_n320 B=$abc$2385$new_n436 Y=$abc$2385$new_n441
+.gate MUX A=$abc$2385$new_n440 B=$abc$2385$new_n441 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[1]
+.gate ORNOT A=:1.test_1[2] B=$abc$2385$new_n83 Y=$abc$2385$new_n443
+.gate ANDNOT A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n444
+.gate XNOR A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n445
+.gate NAND A=$abc$2385$new_n435 B=$abc$2385$new_n445 Y=$abc$2385$new_n446
+.gate ORNOT A=$abc$2385$new_n435 B=$abc$2385$new_n308 Y=$abc$2385$new_n447
+.gate AND A=$abc$2385$new_n74 B=$abc$2385$new_n446 Y=$abc$2385$new_n448
+.gate NAND A=$abc$2385$new_n447 B=$abc$2385$new_n448 Y=$abc$2385$new_n449
+.gate AND A=$abc$2385$new_n443 B=$abc$2385$new_n449 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[2]
+.gate ORNOT A=:1.test_1[3] B=$abc$2385$new_n83 Y=$abc$2385$new_n451
+.gate AND A=$abc$2385$new_n435 B=$abc$2385$new_n444 Y=$abc$2385$new_n452
+.gate AND A=$abc$2385$new_n304 B=$abc$2385$new_n452 Y=$abc$2385$new_n453
+.gate XNOR A=$abc$2385$new_n305 B=$abc$2385$new_n452 Y=$abc$2385$new_n454
+.gate MUX A=$abc$2385$new_n451 B=$abc$2385$new_n454 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[3]
+.gate ORNOT A=:1.test_1[4] B=$abc$2385$new_n83 Y=$abc$2385$new_n456
+.gate ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n457
+.gate XNOR A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n458
+.gate MUX A=$abc$2385$new_n456 B=$abc$2385$new_n458 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[4]
+.gate ORNOT A=:1.test_1[5] B=$abc$2385$new_n83 Y=$abc$2385$new_n460
+.gate OR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n461
+.gate XOR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n462
+.gate NAND A=$abc$2385$new_n74 B=$abc$2385$new_n462 Y=$abc$2385$new_n463
+.gate NAND A=$abc$2385$new_n460 B=$abc$2385$new_n463 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[5]
+.gate NAND A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n465
+.gate OR A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n466
+.gate AND A=$abc$2385$new_n74 B=$abc$2385$new_n466 Y=$abc$2385$new_n467
+.gate NAND A=$abc$2385$new_n465 B=$abc$2385$new_n467 Y=$abc$2385$new_n468
+.gate MUX A=$abc$2385$new_n73 B=$abc$2385$new_n137 S=$abc$2385$new_n76 Y=$abc$2385$new_n469
+.gate OR A=$abc$2385$new_n74 B=$abc$2385$new_n469 Y=$abc$2385$new_n470
+.gate NAND A=$abc$2385$new_n468 B=$abc$2385$new_n470 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[6]
+.gate NAND A=$abc$2385$new_n392 B=$abc$2385$new_n467 Y=$abc$2385$new_n472
+.gate ANDNOT A=$abc$2385$new_n137 B=$abc$2385$new_n76 Y=$abc$2385$new_n473
+.gate XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n473 Y=$abc$2385$new_n474
+.gate AND A=$abc$2385$new_n472 B=$abc$2385$new_n474 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[7]
+.gate AND A=$abc$2385$new_n58 B=$abc$2385$new_n438 Y=:38.Y[0]
+.gate NAND A=in_a_var[1] B=$abc$2385$new_n74 Y=$abc$2385$new_n477
+.gate NAND A=$abc$2385$new_n84 B=$abc$2385$new_n477 Y=:38.Y[1]
+.gate NAND A=in_a_var[2] B=$abc$2385$new_n74 Y=$abc$2385$new_n479
+.gate NAND A=$abc$2385$new_n92 B=$abc$2385$new_n479 Y=:38.Y[2]
+.gate NAND A=in_a_var[3] B=$abc$2385$new_n74 Y=$abc$2385$new_n481
+.gate NAND A=$abc$2385$new_n104 B=$abc$2385$new_n481 Y=:38.Y[3]
+.gate NAND A=in_a_var[4] B=$abc$2385$new_n74 Y=$abc$2385$new_n483
+.gate NAND A=$abc$2385$new_n116 B=$abc$2385$new_n483 Y=:38.Y[4]
+.gate NAND A=in_a_var[5] B=$abc$2385$new_n74 Y=$abc$2385$new_n485
+.gate NAND A=$abc$2385$new_n127 B=$abc$2385$new_n485 Y=:38.Y[5]
+.gate NAND A=in_a_var[6] B=$abc$2385$new_n74 Y=$abc$2385$new_n487
+.gate NAND A=$abc$2385$new_n137 B=$abc$2385$new_n487 Y=:38.Y[6]
+.gate NAND A=in_a_var[7] B=$abc$2385$new_n74 Y=$abc$2385$new_n489
+.gate NAND A=$abc$2385$new_n150 B=$abc$2385$new_n489 Y=:38.Y[7]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] Q=out_var[0]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] Q=out_var[1]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] Q=out_var[2]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] Q=out_var[3]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] Q=out_var[4]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] Q=out_var[5]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] Q=out_var[6]
+.gate DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] Q=out_var[7]
+.gate DFF C=clk D=:38.Y[0] Q=:1.test_1[0]
+.gate DFF C=clk D=:38.Y[1] Q=:1.test_1[1]
+.gate DFF C=clk D=:38.Y[2] Q=:1.test_1[2]
+.gate DFF C=clk D=:38.Y[3] Q=:1.test_1[3]
+.gate DFF C=clk D=:38.Y[4] Q=:1.test_1[4]
+.gate DFF C=clk D=:38.Y[5] Q=:1.test_1[5]
+.gate DFF C=clk D=:38.Y[6] Q=:1.test_1[6]
+.gate DFF C=clk D=:38.Y[7] Q=:1.test_1[7]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[0] Q=:1.test_2[0]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[1] Q=:1.test_2[1]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[2] Q=:1.test_2[2]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[3] Q=:1.test_2[3]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[4] Q=:1.test_2[4]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[5] Q=:1.test_2[5]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[6] Q=:1.test_2[6]
+.gate DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[7] Q=:1.test_2[7]
+.gateinit :1.test_2[7]=0
+.gateinit :1.test_2[6]=0
+.gateinit :1.test_2[5]=0
+.gateinit :1.test_2[4]=0
+.gateinit :1.test_2[3]=0
+.gateinit :1.test_2[2]=0
+.gateinit :1.test_2[1]=0
+.gateinit :1.test_2[0]=0
+.gateinit :1.test_1[7]=1
+.gateinit :1.test_1[6]=1
+.gateinit :1.test_1[5]=1
+.gateinit :1.test_1[4]=1
+.gateinit :1.test_1[3]=1
+.gateinit :1.test_1[2]=1
+.gateinit :1.test_1[1]=1
+.gateinit :1.test_1[0]=1
+.end

tests/blif/gatesi.blif.ok

@@ -0,0 +1,484 @@
+# Generated by Yosys
+
+.model test
+.inputs clk in_a_var[0] in_a_var[1] in_a_var[2] in_a_var[3] in_a_var[4] in_a_var[5] in_a_var[6] in_a_var[7] in_b_var[0] in_b_var[1] in_b_var[2] in_b_var[3] in_b_var[4] in_b_var[5] in_b_var[6] in_b_var[7]
+.outputs out_var[0] out_var[1] out_var[2] out_var[3] out_var[4] out_var[5] out_var[6] out_var[7]
+.names $false
+.names $true
+1
+.names $undef
+.subckt ORNOT A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n57
+.subckt NOT A=$abc$2385$new_n65 Y=$abc$2385$new_n66
+.subckt XNOR A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$auto$maccmap.cc:240:synth$253.P[1]
+.subckt NAND A=:1.test_1[0] B=:1.test_2[0] Y=$abc$2385$new_n157
+.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n91 Y=$abc$2385$new_n158
+.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n64 Y=$abc$2385$new_n159
+.subckt AND A=:1.test_2[1] B=$abc$2385$new_n65 Y=$abc$2385$new_n160
+.subckt ORNOT A=$abc$2385$new_n160 B=:1.test_1[0] Y=$abc$2385$new_n161
+.subckt AND A=:1.test_2[2] B=$abc$2385$new_n161 Y=$abc$2385$new_n162
+.subckt ANDNOT A=:1.test_1[1] B=:1.test_1[0] Y=$abc$2385$new_n163
+.subckt ANDNOT A=:1.test_2[2] B=:1.test_1[0] Y=$abc$2385$new_n164
+.subckt XNOR A=$abc$2385$new_n160 B=$abc$2385$new_n164 Y=$abc$2385$new_n165
+.subckt AND A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n67
+.subckt MUX A=$abc$2385$new_n160 B=$abc$2385$new_n165 S=:1.test_2[2] Y=$abc$2385$new_n166
+.subckt ORNOT A=:1.test_2[0] B=:1.test_1[0] Y=$abc$2385$new_n167
+.subckt AND A=$abc$2385$new_n159 B=$abc$2385$new_n167 Y=$abc$2385$new_n168
+.subckt AND A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n169
+.subckt XOR A=$abc$2385$new_n166 B=$abc$2385$new_n168 Y=$abc$2385$new_n170
+.subckt AND A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n171
+.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n103 Y=$abc$2385$new_n172
+.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n91 Y=$abc$2385$new_n173
+.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n103 Y=$abc$2385$new_n174
+.subckt AND A=$abc$2385$new_n158 B=$abc$2385$new_n174 Y=$abc$2385$new_n175
+.subckt AND A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n68
+.subckt XOR A=$abc$2385$new_n172 B=$abc$2385$new_n173 Y=$abc$2385$new_n176
+.subckt NAND A=:1.test_2[2] B=$abc$2385$new_n65 Y=$abc$2385$new_n177
+.subckt AND A=:1.test_1[0] B=:1.test_2[3] Y=$abc$2385$new_n178
+.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n177 Y=$abc$2385$new_n179
+.subckt XNOR A=$abc$2385$new_n177 B=$abc$2385$new_n178 Y=$abc$2385$new_n180
+.subckt NAND A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n181
+.subckt XOR A=$abc$2385$new_n162 B=$abc$2385$new_n180 Y=$abc$2385$new_n182
+.subckt NAND A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n183
+.subckt XOR A=$abc$2385$new_n176 B=$abc$2385$new_n182 Y=$abc$2385$new_n184
+.subckt NAND A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n185
+.subckt AND A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n69
+.subckt XOR A=$abc$2385$new_n171 B=$abc$2385$new_n184 Y=$abc$2385$new_n186
+.subckt NAND A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n187
+.subckt NAND A=$abc$2385$new_n185 B=$abc$2385$new_n187 Y=$abc$2385$new_n188
+.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n115 Y=$abc$2385$new_n189
+.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n115 Y=$abc$2385$new_n190
+.subckt NAND A=$abc$2385$new_n172 B=$abc$2385$new_n190 Y=$abc$2385$new_n191
+.subckt XOR A=$abc$2385$new_n174 B=$abc$2385$new_n189 Y=$abc$2385$new_n192
+.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n91 Y=$abc$2385$new_n193
+.subckt NAND A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n194
+.subckt XOR A=$abc$2385$new_n192 B=$abc$2385$new_n193 Y=$abc$2385$new_n195
+.subckt AND A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n70
+.subckt AND A=:1.test_2[3] B=$abc$2385$new_n179 Y=$abc$2385$new_n196
+.subckt NAND A=:1.test_2[3] B=$abc$2385$new_n65 Y=$abc$2385$new_n197
+.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n197 Y=$abc$2385$new_n198
+.subckt AND A=:1.test_2[4] B=$abc$2385$new_n198 Y=$abc$2385$new_n199
+.subckt NAND A=:1.test_2[3] B=$abc$2385$new_n163 Y=$abc$2385$new_n200
+.subckt NAND A=$abc$2385$new_n199 B=$abc$2385$new_n200 Y=$abc$2385$new_n201
+.subckt ORNOT A=:1.test_2[4] B=$abc$2385$new_n197 Y=$abc$2385$new_n202
+.subckt AND A=$abc$2385$new_n201 B=$abc$2385$new_n202 Y=$abc$2385$new_n203
+.subckt NAND A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n204
+.subckt XOR A=$abc$2385$new_n175 B=$abc$2385$new_n203 Y=$abc$2385$new_n205
+.subckt AND A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n71
+.subckt NAND A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n206
+.subckt XOR A=$abc$2385$new_n196 B=$abc$2385$new_n205 Y=$abc$2385$new_n207
+.subckt AND A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n208
+.subckt XOR A=$abc$2385$new_n195 B=$abc$2385$new_n207 Y=$abc$2385$new_n209
+.subckt NAND A=$abc$2385$new_n181 B=$abc$2385$new_n183 Y=$abc$2385$new_n210
+.subckt AND A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n211
+.subckt XOR A=$abc$2385$new_n209 B=$abc$2385$new_n210 Y=$abc$2385$new_n212
+.subckt AND A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n213
+.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n77 Y=$abc$2385$new_n214
+.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n91 Y=$abc$2385$new_n215
+.subckt XNOR A=:1.test_1[6] B=$abc$2385$new_n70 Y=$abc$2385$new_n72
+.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n103 Y=$abc$2385$new_n216
+.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n115 Y=$abc$2385$new_n217
+.subckt NAND A=$abc$2385$new_n174 B=$abc$2385$new_n217 Y=$abc$2385$new_n218
+.subckt XOR A=$abc$2385$new_n190 B=$abc$2385$new_n216 Y=$abc$2385$new_n219
+.subckt NAND A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n220
+.subckt XOR A=$abc$2385$new_n215 B=$abc$2385$new_n219 Y=$abc$2385$new_n221
+.subckt AND A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n222
+.subckt XOR A=$abc$2385$new_n214 B=$abc$2385$new_n221 Y=$abc$2385$new_n223
+.subckt NAND A=:1.test_2[4] B=$abc$2385$new_n65 Y=$abc$2385$new_n224
+.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n224 Y=$abc$2385$new_n225
+.subckt NOT A=$abc$2385$new_n72 Y=$abc$2385$new_n73
+.subckt AND A=:1.test_2[5] B=$abc$2385$new_n225 Y=$abc$2385$new_n226
+.subckt NAND A=:1.test_2[4] B=$abc$2385$new_n163 Y=$abc$2385$new_n227
+.subckt NAND A=$abc$2385$new_n226 B=$abc$2385$new_n227 Y=$abc$2385$new_n228
+.subckt ORNOT A=:1.test_2[5] B=$abc$2385$new_n224 Y=$abc$2385$new_n229
+.subckt AND A=$abc$2385$new_n228 B=$abc$2385$new_n229 Y=$abc$2385$new_n230
+.subckt NAND A=$abc$2385$new_n191 B=$abc$2385$new_n194 Y=$abc$2385$new_n231
+.subckt NAND A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n232
+.subckt XOR A=$abc$2385$new_n230 B=$abc$2385$new_n231 Y=$abc$2385$new_n233
+.subckt NAND A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n234
+.subckt XOR A=$abc$2385$new_n199 B=$abc$2385$new_n233 Y=$abc$2385$new_n235
+.subckt AND A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n74
+.subckt AND A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n236
+.subckt XOR A=$abc$2385$new_n223 B=$abc$2385$new_n235 Y=$abc$2385$new_n237
+.subckt NAND A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n238
+.subckt XOR A=$abc$2385$new_n208 B=$abc$2385$new_n237 Y=$abc$2385$new_n239
+.subckt NAND A=$abc$2385$new_n204 B=$abc$2385$new_n206 Y=$abc$2385$new_n240
+.subckt NAND A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n241
+.subckt XOR A=$abc$2385$new_n239 B=$abc$2385$new_n240 Y=$abc$2385$new_n242
+.subckt AND A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n243
+.subckt XOR A=$abc$2385$new_n211 B=$abc$2385$new_n242 Y=$abc$2385$new_n244
+.subckt NAND A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n245
+.subckt XNOR A=:1.test_1[7] B=$abc$2385$new_n71 Y=$abc$2385$new_n75
+.subckt AND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n246
+.subckt NAND A=:1.test_2[0] B=$abc$2385$new_n163 Y=$abc$2385$new_n247
+.subckt XOR A=$abc$2385$new_n158 B=$abc$2385$new_n170 Y=$abc$2385$new_n248
+.subckt AND A=$abc$2385$new_n246 B=$abc$2385$new_n248 Y=$abc$2385$new_n249
+.subckt XOR A=$abc$2385$new_n169 B=$abc$2385$new_n186 Y=$abc$2385$new_n250
+.subckt AND A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n251
+.subckt XOR A=$abc$2385$new_n188 B=$abc$2385$new_n212 Y=$abc$2385$new_n252
+.subckt AND A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n253
+.subckt NAND A=$abc$2385$new_n244 B=$abc$2385$new_n253 Y=$abc$2385$new_n254
+.subckt XNOR A=$abc$2385$new_n213 B=$abc$2385$new_n244 Y=$abc$2385$new_n255
+.subckt ORNOT A=in_a_var[0] B=:1.test_1[0] Y=$abc$2385$new_n58
+.subckt ANDNOT A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n76
+.subckt NAND A=$abc$2385$new_n245 B=$abc$2385$new_n254 Y=$abc$2385$new_n256
+.subckt NAND A=$abc$2385$new_n238 B=$abc$2385$new_n241 Y=$abc$2385$new_n257
+.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n72 Y=$abc$2385$new_n258
+.subckt ORNOT A=$abc$2385$new_n77 B=:1.test_2[1] Y=$abc$2385$new_n259
+.subckt ANDNOT A=:1.test_2[1] B=$abc$2385$new_n72 Y=$abc$2385$new_n260
+.subckt NAND A=$abc$2385$new_n214 B=$abc$2385$new_n260 Y=$abc$2385$new_n261
+.subckt XNOR A=$abc$2385$new_n258 B=$abc$2385$new_n259 Y=$abc$2385$new_n262
+.subckt ANDNOT A=:1.test_2[4] B=$abc$2385$new_n91 Y=$abc$2385$new_n263
+.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n103 Y=$abc$2385$new_n264
+.subckt ANDNOT A=:1.test_2[3] B=$abc$2385$new_n115 Y=$abc$2385$new_n265
+.subckt XNOR A=:1.test_1[5] B=$abc$2385$new_n69 Y=$abc$2385$new_n77
+.subckt NAND A=$abc$2385$new_n216 B=$abc$2385$new_n265 Y=$abc$2385$new_n266
+.subckt XOR A=$abc$2385$new_n217 B=$abc$2385$new_n264 Y=$abc$2385$new_n267
+.subckt NAND A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n268
+.subckt XOR A=$abc$2385$new_n263 B=$abc$2385$new_n267 Y=$abc$2385$new_n269
+.subckt AND A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n270
+.subckt XOR A=$abc$2385$new_n262 B=$abc$2385$new_n269 Y=$abc$2385$new_n271
+.subckt NAND A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n272
+.subckt XOR A=$abc$2385$new_n222 B=$abc$2385$new_n271 Y=$abc$2385$new_n273
+.subckt NAND A=:1.test_2[5] B=$abc$2385$new_n65 Y=$abc$2385$new_n274
+.subckt NAND A=:1.test_1[0] B=$abc$2385$new_n274 Y=$abc$2385$new_n275
+.subckt NOR A=:1.test_1[3] B=:1.test_1[4] Y=$abc$2385$new_n78
+.subckt AND A=:1.test_2[6] B=$abc$2385$new_n275 Y=$abc$2385$new_n276
+.subckt NAND A=:1.test_2[5] B=$abc$2385$new_n163 Y=$abc$2385$new_n277
+.subckt NAND A=:1.test_2[6] B=$abc$2385$new_n65 Y=$abc$2385$new_n278
+.subckt NAND A=$abc$2385$new_n276 B=$abc$2385$new_n277 Y=$abc$2385$new_n279
+.subckt ORNOT A=:1.test_2[6] B=$abc$2385$new_n274 Y=$abc$2385$new_n280
+.subckt AND A=$abc$2385$new_n279 B=$abc$2385$new_n280 Y=$abc$2385$new_n281
+.subckt NAND A=$abc$2385$new_n218 B=$abc$2385$new_n220 Y=$abc$2385$new_n282
+.subckt NAND A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n283
+.subckt XOR A=$abc$2385$new_n281 B=$abc$2385$new_n282 Y=$abc$2385$new_n284
+.subckt NAND A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n285
+.subckt AND A=$abc$2385$new_n63 B=$abc$2385$new_n78 Y=$abc$2385$new_n79
+.subckt XOR A=$abc$2385$new_n226 B=$abc$2385$new_n284 Y=$abc$2385$new_n286
+.subckt NAND A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n287
+.subckt XOR A=$abc$2385$new_n273 B=$abc$2385$new_n286 Y=$abc$2385$new_n288
+.subckt NAND A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n289
+.subckt XOR A=$abc$2385$new_n236 B=$abc$2385$new_n288 Y=$abc$2385$new_n290
+.subckt NAND A=$abc$2385$new_n232 B=$abc$2385$new_n234 Y=$abc$2385$new_n291
+.subckt NAND A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n292
+.subckt XOR A=$abc$2385$new_n290 B=$abc$2385$new_n291 Y=$abc$2385$new_n293
+.subckt NAND A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n294
+.subckt XOR A=$abc$2385$new_n257 B=$abc$2385$new_n293 Y=$abc$2385$new_n295
+.subckt ANDNOT A=$abc$2385$new_n79 B=:1.test_1[2] Y=$abc$2385$new_n80
+.subckt NAND A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n296
+.subckt XOR A=$abc$2385$new_n243 B=$abc$2385$new_n295 Y=$abc$2385$new_n297
+.subckt NAND A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n298
+.subckt XNOR A=$abc$2385$new_n256 B=$abc$2385$new_n297 Y=$abc$2385$new_n299
+.subckt NAND A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n300
+.subckt OR A=$abc$2385$new_n73 B=$abc$2385$new_n299 Y=$abc$2385$new_n301
+.subckt XOR A=$abc$2385$new_n253 B=$abc$2385$new_n255 Y=$abc$2385$new_n302
+.subckt XNOR A=$abc$2385$new_n251 B=$abc$2385$new_n252 Y=$abc$2385$new_n303
+.subckt XOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n304
+.subckt XNOR A=$abc$2385$new_n249 B=$abc$2385$new_n250 Y=$abc$2385$new_n305
+.subckt AND A=$abc$2385$new_n77 B=$abc$2385$new_n80 Y=$abc$2385$new_n81
+.subckt NAND A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n306
+.subckt OR A=$abc$2385$new_n103 B=$abc$2385$new_n304 Y=$abc$2385$new_n307
+.subckt XNOR A=$abc$2385$new_n247 B=$abc$2385$new_n248 Y=$abc$2385$new_n308
+.subckt NAND A=:1.test_1[0] B=:1.test_2[1] Y=$abc$2385$new_n309
+.subckt ANDNOT A=:1.test_2[0] B=$abc$2385$new_n64 Y=$abc$2385$new_n310
+.subckt XNOR A=$abc$2385$new_n309 B=$abc$2385$new_n310 Y=$abc$2385$new_n311
+.subckt NAND A=$abc$2385$new_n66 B=$abc$2385$new_n311 Y=$abc$2385$new_n312
+.subckt OR A=:1.test_2[1] B=$abc$2385$new_n157 Y=$abc$2385$new_n313
+.subckt NAND A=$abc$2385$new_n312 B=$abc$2385$new_n313 Y=$abc$2385$new_n314
+.subckt OR A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n315
+.subckt NAND A=$abc$2385$new_n75 B=$abc$2385$new_n81 Y=$abc$2385$new_n82
+.subckt NAND A=$abc$2385$new_n91 B=$abc$2385$new_n315 Y=$abc$2385$new_n316
+.subckt NAND A=$abc$2385$new_n308 B=$abc$2385$new_n314 Y=$abc$2385$new_n317
+.subckt NAND A=$abc$2385$new_n316 B=$abc$2385$new_n317 Y=$abc$2385$new_n318
+.subckt NAND A=$abc$2385$new_n307 B=$abc$2385$new_n318 Y=$abc$2385$new_n319
+.subckt NAND A=$abc$2385$new_n247 B=$abc$2385$new_n311 Y=$abc$2385$new_n320
+.subckt NAND A=$abc$2385$new_n306 B=$abc$2385$new_n319 Y=$abc$2385$new_n321
+.subckt ORNOT A=$abc$2385$new_n115 B=$abc$2385$new_n303 Y=$abc$2385$new_n322
+.subckt ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n115 Y=$abc$2385$new_n323
+.subckt NAND A=$abc$2385$new_n321 B=$abc$2385$new_n322 Y=$abc$2385$new_n324
+.subckt NAND A=$abc$2385$new_n323 B=$abc$2385$new_n324 Y=$abc$2385$new_n325
+.subckt OR A=$abc$2385$new_n73 B=$abc$2385$new_n82 Y=$abc$2385$new_n83
+.subckt NAND A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n326
+.subckt NAND A=$abc$2385$new_n302 B=$abc$2385$new_n326 Y=$abc$2385$new_n327
+.subckt OR A=$abc$2385$new_n77 B=$abc$2385$new_n325 Y=$abc$2385$new_n328
+.subckt AND A=$abc$2385$new_n327 B=$abc$2385$new_n328 Y=$abc$2385$new_n329
+.subckt NAND A=$abc$2385$new_n300 B=$abc$2385$new_n329 Y=$abc$2385$new_n330
+.subckt AND A=$abc$2385$new_n301 B=$abc$2385$new_n330 Y=$abc$2385$new_n331
+.subckt NAND A=$abc$2385$new_n75 B=$abc$2385$new_n331 Y=$abc$2385$new_n332
+.subckt OR A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n333
+.subckt NAND A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n334
+.subckt OR A=in_b_var[4] B=$abc$2385$new_n303 Y=$abc$2385$new_n335
+.subckt AND A=$abc$2385$new_n66 B=$abc$2385$new_n83 Y=$abc$2385$new_n84
+.subckt AND A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n336
+.subckt OR A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n337
+.subckt ANDNOT A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n338
+.subckt XNOR A=in_b_var[2] B=$abc$2385$new_n308 Y=$abc$2385$new_n339
+.subckt NAND A=in_b_var[3] B=$abc$2385$new_n305 Y=$abc$2385$new_n340
+.subckt XNOR A=in_b_var[3] B=$abc$2385$new_n304 Y=$abc$2385$new_n341
+.subckt AND A=$abc$2385$new_n339 B=$abc$2385$new_n341 Y=$abc$2385$new_n342
+.subckt NAND A=$abc$2385$new_n336 B=$abc$2385$new_n342 Y=$abc$2385$new_n343
+.subckt NAND A=$abc$2385$new_n337 B=$abc$2385$new_n338 Y=$abc$2385$new_n344
+.subckt AND A=$abc$2385$new_n340 B=$abc$2385$new_n344 Y=$abc$2385$new_n345
+.subckt ORNOT A=$abc$2385$new_n84 B=in_a_var[1] Y=$abc$2385$new_n85
+.subckt AND A=$abc$2385$new_n343 B=$abc$2385$new_n345 Y=$abc$2385$new_n346
+.subckt AND A=in_b_var[0] B=$abc$2385$new_n157 Y=$abc$2385$new_n347
+.subckt XOR A=in_b_var[1] B=$abc$2385$new_n320 Y=$abc$2385$new_n348
+.subckt AND A=$abc$2385$new_n342 B=$abc$2385$new_n348 Y=$abc$2385$new_n349
+.subckt NAND A=$abc$2385$new_n347 B=$abc$2385$new_n349 Y=$abc$2385$new_n350
+.subckt NAND A=$abc$2385$new_n346 B=$abc$2385$new_n350 Y=$abc$2385$new_n351
+.subckt NAND A=$abc$2385$new_n335 B=$abc$2385$new_n351 Y=$abc$2385$new_n352
+.subckt NAND A=$abc$2385$new_n334 B=$abc$2385$new_n352 Y=$abc$2385$new_n353
+.subckt NAND A=$abc$2385$new_n333 B=$abc$2385$new_n353 Y=$abc$2385$new_n354
+.subckt NAND A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n355
+.subckt XNOR A=:1.test_1[0] B=in_a_var[0] Y=$abc$2385$new_n59
+.subckt XNOR A=in_a_var[1] B=$abc$2385$new_n84 Y=$abc$2385$new_n86
+.subckt NAND A=in_b_var[5] B=$abc$2385$new_n302 Y=$abc$2385$new_n356
+.subckt AND A=$abc$2385$new_n355 B=$abc$2385$new_n356 Y=$abc$2385$new_n357
+.subckt NAND A=$abc$2385$new_n354 B=$abc$2385$new_n357 Y=$abc$2385$new_n358
+.subckt AND A=$abc$2385$new_n157 B=$abc$2385$new_n320 Y=$abc$2385$new_n359
+.subckt ANDNOT A=$abc$2385$new_n359 B=$abc$2385$new_n308 Y=$abc$2385$new_n360
+.subckt AND A=$abc$2385$new_n305 B=$abc$2385$new_n360 Y=$abc$2385$new_n361
+.subckt AND A=$abc$2385$new_n303 B=$abc$2385$new_n361 Y=$abc$2385$new_n362
+.subckt AND A=$abc$2385$new_n302 B=$abc$2385$new_n362 Y=$abc$2385$new_n363
+.subckt NAND A=$abc$2385$new_n299 B=$abc$2385$new_n363 Y=$abc$2385$new_n364
+.subckt AND A=$abc$2385$new_n296 B=$abc$2385$new_n298 Y=$abc$2385$new_n365
+.subckt NAND A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n87
+.subckt AND A=$abc$2385$new_n289 B=$abc$2385$new_n292 Y=$abc$2385$new_n366
+.subckt OR A=:1.test_2[0] B=$abc$2385$new_n75 Y=$abc$2385$new_n367
+.subckt AND A=$abc$2385$new_n261 B=$abc$2385$new_n367 Y=$abc$2385$new_n368
+.subckt XNOR A=$abc$2385$new_n270 B=$abc$2385$new_n368 Y=$abc$2385$new_n369
+.subckt XNOR A=$abc$2385$new_n276 B=$abc$2385$new_n369 Y=$abc$2385$new_n370
+.subckt ANDNOT A=:1.test_2[2] B=$abc$2385$new_n77 Y=$abc$2385$new_n371
+.subckt ANDNOT A=:1.test_2[5] B=$abc$2385$new_n91 Y=$abc$2385$new_n372
+.subckt ANDNOT A=:1.test_2[4] B=$abc$2385$new_n103 Y=$abc$2385$new_n373
+.subckt XNOR A=$abc$2385$new_n372 B=$abc$2385$new_n373 Y=$abc$2385$new_n374
+.subckt XNOR A=$abc$2385$new_n371 B=$abc$2385$new_n374 Y=$abc$2385$new_n375
+.subckt XNOR A=in_b_var[1] B=$abc$2385$new_n86 Y=$abc$2385$new_n88
+.subckt XOR A=$abc$2385$new_n260 B=$abc$2385$new_n265 Y=$abc$2385$new_n376
+.subckt XNOR A=$abc$2385$new_n375 B=$abc$2385$new_n376 Y=$abc$2385$new_n377
+.subckt NAND A=$abc$2385$new_n266 B=$abc$2385$new_n268 Y=$abc$2385$new_n378
+.subckt ANDNOT A=:1.test_2[7] B=:1.test_1[0] Y=$abc$2385$new_n379
+.subckt XNOR A=$abc$2385$new_n278 B=$abc$2385$new_n379 Y=$abc$2385$new_n380
+.subckt XNOR A=$abc$2385$new_n75 B=$abc$2385$new_n380 Y=$abc$2385$new_n381
+.subckt XNOR A=$abc$2385$new_n378 B=$abc$2385$new_n381 Y=$abc$2385$new_n382
+.subckt XNOR A=$abc$2385$new_n377 B=$abc$2385$new_n382 Y=$abc$2385$new_n383
+.subckt XNOR A=$abc$2385$new_n370 B=$abc$2385$new_n383 Y=$abc$2385$new_n384
+.subckt NAND A=$abc$2385$new_n283 B=$abc$2385$new_n285 Y=$abc$2385$new_n385
+.subckt ANDNOT A=$abc$2385$new_n62 B=$abc$2385$new_n88 Y=$abc$2385$new_n89
+.subckt AND A=$abc$2385$new_n272 B=$abc$2385$new_n287 Y=$abc$2385$new_n386
+.subckt XNOR A=$abc$2385$new_n385 B=$abc$2385$new_n386 Y=$abc$2385$new_n387
+.subckt XNOR A=$abc$2385$new_n384 B=$abc$2385$new_n387 Y=$abc$2385$new_n388
+.subckt XNOR A=$abc$2385$new_n366 B=$abc$2385$new_n388 Y=$abc$2385$new_n389
+.subckt XNOR A=:1.test_2[7] B=$abc$2385$new_n294 Y=$abc$2385$new_n390
+.subckt XNOR A=$abc$2385$new_n389 B=$abc$2385$new_n390 Y=$abc$2385$new_n391
+.subckt XNOR A=$abc$2385$new_n365 B=$abc$2385$new_n391 Y=$abc$2385$new_n392
+.subckt OR A=in_b_var[6] B=$abc$2385$new_n299 Y=$abc$2385$new_n393
+.subckt ORNOT A=in_b_var[6] B=in_a_var[6] Y=$abc$2385$new_n394
+.subckt ORNOT A=in_a_var[5] B=in_b_var[5] Y=$abc$2385$new_n395
+.subckt AND A=$abc$2385$new_n85 B=$abc$2385$new_n87 Y=$abc$2385$new_n90
+.subckt ORNOT A=in_b_var[5] B=in_a_var[5] Y=$abc$2385$new_n396
+.subckt ORNOT A=in_b_var[4] B=in_a_var[4] Y=$abc$2385$new_n397
+.subckt AND A=$abc$2385$new_n396 B=$abc$2385$new_n397 Y=$abc$2385$new_n398
+.subckt ORNOT A=in_b_var[2] B=in_a_var[2] Y=$abc$2385$new_n399
+.subckt ORNOT A=in_b_var[3] B=in_a_var[3] Y=$abc$2385$new_n400
+.subckt NAND A=$abc$2385$new_n399 B=$abc$2385$new_n400 Y=$abc$2385$new_n401
+.subckt ORNOT A=in_a_var[3] B=in_b_var[3] Y=$abc$2385$new_n402
+.subckt NAND A=$abc$2385$new_n401 B=$abc$2385$new_n402 Y=$abc$2385$new_n403
+.subckt ORNOT A=in_a_var[2] B=in_b_var[2] Y=$abc$2385$new_n404
+.subckt NAND A=$abc$2385$new_n402 B=$abc$2385$new_n404 Y=$abc$2385$new_n405
+.subckt XNOR A=:1.test_1[2] B=$abc$2385$new_n64 Y=$abc$2385$new_n91
+.subckt NOR A=$abc$2385$new_n401 B=$abc$2385$new_n405 Y=$abc$2385$new_n406
+.subckt ORNOT A=in_a_var[0] B=in_b_var[0] Y=$abc$2385$new_n407
+.subckt ORNOT A=in_a_var[1] B=in_b_var[1] Y=$abc$2385$new_n408
+.subckt NAND A=$abc$2385$new_n407 B=$abc$2385$new_n408 Y=$abc$2385$new_n409
+.subckt ORNOT A=in_b_var[1] B=in_a_var[1] Y=$abc$2385$new_n410
+.subckt NAND A=$abc$2385$new_n409 B=$abc$2385$new_n410 Y=$abc$2385$new_n411
+.subckt NAND A=$abc$2385$new_n406 B=$abc$2385$new_n411 Y=$abc$2385$new_n412
+.subckt NAND A=$abc$2385$new_n403 B=$abc$2385$new_n412 Y=$abc$2385$new_n413
+.subckt ORNOT A=in_a_var[4] B=in_b_var[4] Y=$abc$2385$new_n414
+.subckt NAND A=$abc$2385$new_n413 B=$abc$2385$new_n414 Y=$abc$2385$new_n415
+.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n91 Y=$abc$2385$new_n92
+.subckt NAND A=$abc$2385$new_n398 B=$abc$2385$new_n415 Y=$abc$2385$new_n416
+.subckt NAND A=$abc$2385$new_n395 B=$abc$2385$new_n416 Y=$abc$2385$new_n417
+.subckt NAND A=$abc$2385$new_n394 B=$abc$2385$new_n417 Y=$abc$2385$new_n418
+.subckt NAND A=$abc$2385$new_n394 B=$abc$2385$new_n395 Y=$abc$2385$new_n419
+.subckt NOR A=$abc$2385$new_n409 B=$abc$2385$new_n419 Y=$abc$2385$new_n420
+.subckt AND A=$abc$2385$new_n398 B=$abc$2385$new_n420 Y=$abc$2385$new_n421
+.subckt ORNOT A=in_b_var[0] B=in_a_var[0] Y=$abc$2385$new_n422
+.subckt AND A=$abc$2385$new_n410 B=$abc$2385$new_n414 Y=$abc$2385$new_n423
+.subckt AND A=$abc$2385$new_n422 B=$abc$2385$new_n423 Y=$abc$2385$new_n424
+.subckt AND A=$abc$2385$new_n406 B=$abc$2385$new_n424 Y=$abc$2385$new_n425
+.subckt ORNOT A=$abc$2385$new_n92 B=in_a_var[2] Y=$abc$2385$new_n93
+.subckt NAND A=$abc$2385$new_n421 B=$abc$2385$new_n425 Y=$abc$2385$new_n426
+.subckt ORNOT A=in_a_var[6] B=in_b_var[6] Y=$abc$2385$new_n427
+.subckt AND A=$abc$2385$new_n151 B=$abc$2385$new_n427 Y=$abc$2385$new_n428
+.subckt AND A=$abc$2385$new_n426 B=$abc$2385$new_n428 Y=$abc$2385$new_n429
+.subckt AND A=$abc$2385$new_n418 B=$abc$2385$new_n429 Y=$abc$2385$new_n430
+.subckt AND A=$abc$2385$new_n393 B=$abc$2385$new_n430 Y=$abc$2385$new_n431
+.subckt AND A=$abc$2385$new_n392 B=$abc$2385$new_n431 Y=$abc$2385$new_n432
+.subckt AND A=$abc$2385$new_n364 B=$abc$2385$new_n432 Y=$abc$2385$new_n433
+.subckt AND A=$abc$2385$new_n358 B=$abc$2385$new_n433 Y=$abc$2385$new_n434
+.subckt AND A=$abc$2385$new_n332 B=$abc$2385$new_n434 Y=$abc$2385$new_n435
+.subckt XNOR A=in_a_var[2] B=$abc$2385$new_n92 Y=$abc$2385$new_n94
+.subckt AND A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n436
+.subckt XNOR A=$abc$2385$new_n157 B=$abc$2385$new_n435 Y=$abc$2385$new_n437
+.subckt ORNOT A=$abc$2385$new_n74 B=:1.test_1[0] Y=$abc$2385$new_n438
+.subckt MUX A=:1.test_1[0] B=$abc$2385$new_n437 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[0]
+.subckt ORNOT A=:1.test_1[1] B=$abc$2385$new_n83 Y=$abc$2385$new_n440
+.subckt XNOR A=$abc$2385$new_n320 B=$abc$2385$new_n436 Y=$abc$2385$new_n441
+.subckt MUX A=$abc$2385$new_n440 B=$abc$2385$new_n441 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[1]
+.subckt ORNOT A=:1.test_1[2] B=$abc$2385$new_n83 Y=$abc$2385$new_n443
+.subckt ANDNOT A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n444
+.subckt XNOR A=$abc$2385$new_n308 B=$abc$2385$new_n359 Y=$abc$2385$new_n445
+.subckt NAND A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n95
+.subckt NAND A=$abc$2385$new_n435 B=$abc$2385$new_n445 Y=$abc$2385$new_n446
+.subckt ORNOT A=$abc$2385$new_n435 B=$abc$2385$new_n308 Y=$abc$2385$new_n447
+.subckt AND A=$abc$2385$new_n74 B=$abc$2385$new_n446 Y=$abc$2385$new_n448
+.subckt NAND A=$abc$2385$new_n447 B=$abc$2385$new_n448 Y=$abc$2385$new_n449
+.subckt AND A=$abc$2385$new_n443 B=$abc$2385$new_n449 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[2]
+.subckt ORNOT A=:1.test_1[3] B=$abc$2385$new_n83 Y=$abc$2385$new_n451
+.subckt AND A=$abc$2385$new_n435 B=$abc$2385$new_n444 Y=$abc$2385$new_n452
+.subckt AND A=$abc$2385$new_n304 B=$abc$2385$new_n452 Y=$abc$2385$new_n453
+.subckt XNOR A=$abc$2385$new_n305 B=$abc$2385$new_n452 Y=$abc$2385$new_n454
+.subckt MUX A=$abc$2385$new_n451 B=$abc$2385$new_n454 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[3]
+.subckt NAND A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$new_n60
+.subckt XNOR A=in_b_var[2] B=$abc$2385$new_n94 Y=$abc$2385$new_n96
+.subckt ORNOT A=:1.test_1[4] B=$abc$2385$new_n83 Y=$abc$2385$new_n456
+.subckt ORNOT A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n457
+.subckt XNOR A=$abc$2385$new_n303 B=$abc$2385$new_n453 Y=$abc$2385$new_n458
+.subckt MUX A=$abc$2385$new_n456 B=$abc$2385$new_n458 S=$abc$2385$new_n74 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[4]
+.subckt ORNOT A=:1.test_1[5] B=$abc$2385$new_n83 Y=$abc$2385$new_n460
+.subckt OR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n461
+.subckt XOR A=$abc$2385$new_n302 B=$abc$2385$new_n457 Y=$abc$2385$new_n462
+.subckt NAND A=$abc$2385$new_n74 B=$abc$2385$new_n462 Y=$abc$2385$new_n463
+.subckt NAND A=$abc$2385$new_n460 B=$abc$2385$new_n463 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[5]
+.subckt NAND A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n465
+.subckt OR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n97
+.subckt OR A=$abc$2385$new_n299 B=$abc$2385$new_n461 Y=$abc$2385$new_n466
+.subckt AND A=$abc$2385$new_n74 B=$abc$2385$new_n466 Y=$abc$2385$new_n467
+.subckt NAND A=$abc$2385$new_n465 B=$abc$2385$new_n467 Y=$abc$2385$new_n468
+.subckt MUX A=$abc$2385$new_n73 B=$abc$2385$new_n137 S=$abc$2385$new_n76 Y=$abc$2385$new_n469
+.subckt OR A=$abc$2385$new_n74 B=$abc$2385$new_n469 Y=$abc$2385$new_n470
+.subckt NAND A=$abc$2385$new_n468 B=$abc$2385$new_n470 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[6]
+.subckt NAND A=$abc$2385$new_n392 B=$abc$2385$new_n467 Y=$abc$2385$new_n472
+.subckt ANDNOT A=$abc$2385$new_n137 B=$abc$2385$new_n76 Y=$abc$2385$new_n473
+.subckt XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n473 Y=$abc$2385$new_n474
+.subckt AND A=$abc$2385$new_n472 B=$abc$2385$new_n474 Y=$abc$1802$auto$ghdl.cc:825:import_module$22[7]
+.subckt XOR A=$abc$2385$new_n90 B=$abc$2385$new_n96 Y=$abc$2385$new_n98
+.subckt AND A=$abc$2385$new_n58 B=$abc$2385$new_n438 Y=:38.Y[0]
+.subckt NAND A=in_a_var[1] B=$abc$2385$new_n74 Y=$abc$2385$new_n477
+.subckt NAND A=$abc$2385$new_n84 B=$abc$2385$new_n477 Y=:38.Y[1]
+.subckt NAND A=in_a_var[2] B=$abc$2385$new_n74 Y=$abc$2385$new_n479
+.subckt NAND A=$abc$2385$new_n92 B=$abc$2385$new_n479 Y=:38.Y[2]
+.subckt NAND A=in_a_var[3] B=$abc$2385$new_n74 Y=$abc$2385$new_n481
+.subckt NAND A=$abc$2385$new_n104 B=$abc$2385$new_n481 Y=:38.Y[3]
+.subckt NAND A=in_a_var[4] B=$abc$2385$new_n74 Y=$abc$2385$new_n483
+.subckt NAND A=$abc$2385$new_n116 B=$abc$2385$new_n483 Y=:38.Y[4]
+.subckt NAND A=in_a_var[5] B=$abc$2385$new_n74 Y=$abc$2385$new_n485
+.subckt NAND A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$new_n99
+.subckt NAND A=$abc$2385$new_n127 B=$abc$2385$new_n485 Y=:38.Y[5]
+.subckt NAND A=in_a_var[6] B=$abc$2385$new_n74 Y=$abc$2385$new_n487
+.subckt NAND A=$abc$2385$new_n137 B=$abc$2385$new_n487 Y=:38.Y[6]
+.subckt NAND A=in_a_var[7] B=$abc$2385$new_n74 Y=$abc$2385$new_n489
+.subckt NAND A=$abc$2385$new_n150 B=$abc$2385$new_n489 Y=:38.Y[7]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0] Q=out_var[0]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.P[1] Q=out_var[1]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2] Q=out_var[2]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3] Q=out_var[3]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4] Q=out_var[4]
+.subckt XOR A=$abc$2385$new_n89 B=$abc$2385$new_n98 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[2]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5] Q=out_var[5]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6] Q=out_var[6]
+.subckt DFF C=clk D=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7] Q=out_var[7]
+.subckt DFF C=clk D=:38.Y[0] Q=:1.test_1[0]
+.subckt DFF C=clk D=:38.Y[1] Q=:1.test_1[1]
+.subckt DFF C=clk D=:38.Y[2] Q=:1.test_1[2]
+.subckt DFF C=clk D=:38.Y[3] Q=:1.test_1[3]
+.subckt DFF C=clk D=:38.Y[4] Q=:1.test_1[4]
+.subckt DFF C=clk D=:38.Y[5] Q=:1.test_1[5]
+.subckt DFF C=clk D=:38.Y[6] Q=:1.test_1[6]
+.subckt NAND A=$abc$2385$new_n97 B=$abc$2385$new_n99 Y=$abc$2385$new_n101
+.subckt DFF C=clk D=:38.Y[7] Q=:1.test_1[7]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[0] Q=:1.test_2[0]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[1] Q=:1.test_2[1]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[2] Q=:1.test_2[2]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[3] Q=:1.test_2[3]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[4] Q=:1.test_2[4]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[5] Q=:1.test_2[5]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[6] Q=:1.test_2[6]
+.subckt DFF C=clk D=$abc$1802$auto$ghdl.cc:825:import_module$22[7] Q=:1.test_2[7]
+.subckt AND A=$abc$2385$new_n93 B=$abc$2385$new_n95 Y=$abc$2385$new_n102
+.subckt XNOR A=:1.test_1[3] B=$abc$2385$new_n67 Y=$abc$2385$new_n103
+.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n103 Y=$abc$2385$new_n104
+.subckt ORNOT A=$abc$2385$new_n104 B=in_a_var[3] Y=$abc$2385$new_n105
+.subckt XOR A=in_b_var[0] B=$abc$2385$new_n59 Y=$abc$2385$auto$maccmap.cc:114:fulladd$252.Y[0]
+.subckt XNOR A=in_a_var[3] B=$abc$2385$new_n104 Y=$abc$2385$new_n106
+.subckt NAND A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n107
+.subckt XNOR A=in_b_var[3] B=$abc$2385$new_n106 Y=$abc$2385$new_n108
+.subckt OR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n109
+.subckt XOR A=$abc$2385$new_n102 B=$abc$2385$new_n108 Y=$abc$2385$new_n110
+.subckt NAND A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$new_n111
+.subckt XOR A=$abc$2385$new_n101 B=$abc$2385$new_n110 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[3]
+.subckt NAND A=$abc$2385$new_n109 B=$abc$2385$new_n111 Y=$abc$2385$new_n113
+.subckt AND A=$abc$2385$new_n105 B=$abc$2385$new_n107 Y=$abc$2385$new_n114
+.subckt XNOR A=:1.test_1[4] B=$abc$2385$new_n68 Y=$abc$2385$new_n115
+.subckt NAND A=$abc$2385$new_n57 B=$abc$2385$new_n60 Y=$abc$2385$new_n62
+.subckt AND A=$abc$2385$new_n83 B=$abc$2385$new_n115 Y=$abc$2385$new_n116
+.subckt ORNOT A=$abc$2385$new_n116 B=in_a_var[4] Y=$abc$2385$new_n117
+.subckt XNOR A=in_a_var[4] B=$abc$2385$new_n116 Y=$abc$2385$new_n118
+.subckt NAND A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n119
+.subckt XNOR A=in_b_var[4] B=$abc$2385$new_n118 Y=$abc$2385$new_n120
+.subckt OR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n121
+.subckt XOR A=$abc$2385$new_n114 B=$abc$2385$new_n120 Y=$abc$2385$new_n122
+.subckt NAND A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$new_n123
+.subckt XOR A=$abc$2385$new_n113 B=$abc$2385$new_n122 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[4]
+.subckt AND A=$abc$2385$new_n121 B=$abc$2385$new_n123 Y=$abc$2385$new_n125
+.subckt NOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n63
+.subckt AND A=$abc$2385$new_n117 B=$abc$2385$new_n119 Y=$abc$2385$new_n126
+.subckt AND A=$abc$2385$new_n77 B=$abc$2385$new_n83 Y=$abc$2385$new_n127
+.subckt ORNOT A=$abc$2385$new_n127 B=in_a_var[5] Y=$abc$2385$new_n128
+.subckt XNOR A=in_a_var[5] B=$abc$2385$new_n127 Y=$abc$2385$new_n129
+.subckt NAND A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n130
+.subckt XNOR A=in_b_var[5] B=$abc$2385$new_n129 Y=$abc$2385$new_n131
+.subckt OR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n132
+.subckt NAND A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n133
+.subckt XOR A=$abc$2385$new_n126 B=$abc$2385$new_n131 Y=$abc$2385$new_n134
+.subckt XNOR A=$abc$2385$new_n125 B=$abc$2385$new_n134 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[5]
+.subckt AND A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n64
+.subckt AND A=$abc$2385$new_n128 B=$abc$2385$new_n130 Y=$abc$2385$new_n136
+.subckt AND A=$abc$2385$new_n72 B=$abc$2385$new_n82 Y=$abc$2385$new_n137
+.subckt ORNOT A=$abc$2385$new_n137 B=in_a_var[6] Y=$abc$2385$new_n138
+.subckt XNOR A=in_a_var[6] B=$abc$2385$new_n137 Y=$abc$2385$new_n139
+.subckt NAND A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n140
+.subckt XNOR A=in_b_var[6] B=$abc$2385$new_n139 Y=$abc$2385$new_n141
+.subckt OR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n142
+.subckt XOR A=$abc$2385$new_n136 B=$abc$2385$new_n141 Y=$abc$2385$new_n143
+.subckt NAND A=$abc$2385$new_n125 B=$abc$2385$new_n132 Y=$abc$2385$new_n144
+.subckt AND A=$abc$2385$new_n133 B=$abc$2385$new_n144 Y=$abc$2385$new_n145
+.subckt XOR A=:1.test_1[0] B=:1.test_1[1] Y=$abc$2385$new_n65
+.subckt NAND A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$new_n146
+.subckt XOR A=$abc$2385$new_n143 B=$abc$2385$new_n145 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[6]
+.subckt AND A=$abc$2385$new_n142 B=$abc$2385$new_n146 Y=$abc$2385$new_n148
+.subckt AND A=$abc$2385$new_n138 B=$abc$2385$new_n140 Y=$abc$2385$new_n149
+.subckt AND A=$abc$2385$new_n75 B=$abc$2385$new_n83 Y=$abc$2385$new_n150
+.subckt NOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n151
+.subckt XOR A=in_b_var[7] B=in_a_var[7] Y=$abc$2385$new_n152
+.subckt XNOR A=$abc$2385$new_n150 B=$abc$2385$new_n152 Y=$abc$2385$new_n153
+.subckt XNOR A=$abc$2385$new_n149 B=$abc$2385$new_n153 Y=$abc$2385$new_n154
+.subckt XNOR A=$abc$2385$new_n148 B=$abc$2385$new_n154 Y=$abc$2385$auto$maccmap.cc:240:synth$253.Y[7]
+.gateinit :1.test_2[7]=0
+.gateinit :1.test_2[6]=0
+.gateinit :1.test_2[5]=0
+.gateinit :1.test_2[4]=0
+.gateinit :1.test_2[3]=0
+.gateinit :1.test_2[2]=0
+.gateinit :1.test_2[1]=0
+.gateinit :1.test_2[0]=0
+.gateinit :1.test_1[7]=1
+.gateinit :1.test_1[6]=1
+.gateinit :1.test_1[5]=1
+.gateinit :1.test_1[4]=1
+.gateinit :1.test_1[3]=1
+.gateinit :1.test_1[2]=1
+.gateinit :1.test_1[1]=1
+.gateinit :1.test_1[0]=1
+.end

tests/blif/gatesi.ys

@@ -0,0 +1,2 @@
+read_blif gatesi.blif
+write_blif -gatesi gatesi.blif.out

tests/blif/run-test.sh

@@ -3,5 +3,9 @@ source ../common-env.sh
 set -e
 for x in *.ys; do
   echo "Running $x.."
-  ../../yosys -ql ${x%.ys}.log $x
+  ../../yosys --no-version -ql ${x%.ys}.log $x
 done
+
+for x in *.blif; do
+  diff $x.out $x.ok
+done

tests/opt/opt_clean_standalone_wires.ys

@@ -0,0 +1,10 @@
+read_rtlil << EOT
+module \test
+  wire \wire_a
+  wire \wire_f
+  connect \wire_f \wire_a
+end
+EOT
+
+opt_clean
+select -assert-count 0 */*

tests/opt/opt_expr.ys

@@ -319,3 +319,59 @@ check
 equiv_opt -assert opt_expr -keepdc
 design -load postopt
 select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i
+
+###########
+
+design -reset
+read_rtlil <<EOF
+module \top
+  wire width 3 input 2 \binary
+
+  wire width 32 output 3 \y
+
+  cell $pow $0
+    parameter \A_WIDTH 32
+    parameter \B_WIDTH 3
+    parameter \A_SIGNED 1
+    parameter \B_SIGNED 0
+    parameter \Y_WIDTH 32
+    connect \A 2
+    connect \B \binary
+    connect \Y \y
+  end
+end
+EOF
+
+scratchpad -set opt.did_something false
+opt_expr
+scratchpad -assert opt.did_something true
+sat -verify -set binary 0 -prove y 1
+sat -verify -set binary 1 -prove y 2
+sat -verify -set binary 2 -prove y 4
+sat -verify -set binary 3 -prove y 8
+
+###########
+
+design -reset
+read_rtlil <<EOF
+module \top
+  wire width 3 input 2 \binary
+
+  wire width 32 output 3 \y
+
+  cell $pow $0
+    parameter \A_WIDTH 2
+    parameter \B_WIDTH 3
+    parameter \A_SIGNED 1
+    parameter \B_SIGNED 0
+    parameter \Y_WIDTH 32
+    connect \A 2'10
+    connect \B \binary
+    connect \Y \y
+  end
+end
+EOF
+
+scratchpad -set opt.did_something false
+opt_expr
+scratchpad -assert opt.did_something false

tests/pyosys/test_design_run_pass.py

@@ -0,0 +1,20 @@
+from pathlib import Path
+from pyosys import libyosys as ys
+
+__file_dir__ = Path(__file__).absolute().parent
+add_sub = __file_dir__.parent / "arch" / "common" / "add_sub.v"
+
+base = ys.Design()
+base.run_pass(["read_verilog", str(add_sub)])
+base.run_pass("hierarchy -top top")
+base.run_pass(["proc"])
+base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5")
+
+postopt = ys.Design()
+postopt.run_pass("design -load postopt")
+postopt.run_pass(["cd", "top"])
+postopt.run_pass("select -assert-min 25 t:LUT4")
+postopt.run_pass("select -assert-max 26 t:LUT4")
+postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"])
+postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"])
+postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D")

tests/techmap/bug5574.ys

@@ -0,0 +1,11 @@
+# On Linux, with a spawned abc, this message is the error
+# otherwise the error is the failure to load the output.blif
+logger -expect log "ABC: Error: This command can only be applied to an AIG" 1
+logger -expect error "ABC" 1
+read_verilog << EOT
+module fuzz_mwoqk (input i0, output o0);
+  assign o0 = i0 ^ 1;
+endmodule
+EOT
+synth
+abc -script +resub,-K,8;

tests/techmap/lut2mux.ys

@@ -0,0 +1,42 @@
+# Test lut2mux pass using a directly constructed $lut (avoids frontend/synth differences in test-verific)
+
+read_rtlil << EOT
+module \top
+  wire width 2 input 1 \a
+  wire width 1 output 2 \y
+  cell $lut \u_lut
+    parameter \WIDTH 2
+    parameter \LUT 4'0110
+    connect \A \a
+    connect \Y \y
+  end
+end
+EOT
+
+select -assert-count 1 t:$lut
+
+# default mode -> gate-level $_MUX_
+design -save gold
+lut2mux
+rename \top \gate
+select -assert-count 3 gate/t:$_MUX_
+select -assert-count 0 gate/t:$mux
+select -assert-count 0 gate/t:$lut
+
+# -word mode -> word-level $mux
+design -copy-from gold -as top \top
+select -none
+select top
+lut2mux -word
+select -clear
+rename \top \word
+select -assert-count 3 word/t:$mux
+select -assert-count 0 word/t:$_MUX_
+select -assert-count 0 gate/t:$lut
+
+# equivalence
+equiv_make \gate \word equiv
+hierarchy -top equiv
+equiv_simple
+equiv_induct
+equiv_status -assert

tests/techmap/module_not_derived.ys

@@ -0,0 +1,31 @@
+# Test 1: internal cells from alumacc/techmap must not keep module_not_derived.
+read_verilog <<EOF_VERILOG
+module top(a, b, y);
+  input wire [7:0] a;
+  input wire [7:0] b;
+  output wire [7:0] y;
+  assign y = a + b;
+endmodule
+EOF_VERILOG
+
+prep
+alumacc
+techmap -max_iter 1
+
+select -assert-any t:$lcu
+select -assert-count 0 t:$lcu a:module_not_derived %i
+
+design -reset
+# Test 2: public module instances should still keep module_not_derived.
+read_verilog <<EOF_VERILOG
+module mycell(input a, output y);
+	assign y = a;
+endmodule
+
+module top(input a, output y);
+	mycell u0(.a(a), .y(y));
+endmodule
+EOF_VERILOG
+
+hierarchy -top top
+select -assert-any t:mycell a:module_not_derived %i

tests/unit/kernel/rtlilStringTest.cc

@@ -0,0 +1,61 @@
+#include <gtest/gtest.h>
+
+#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+namespace RTLIL {
+
+	TEST(RtlilStrTest, DesignToString) {
+		Design design;
+		Module *mod = design.addModule(ID(my_module));
+		mod->addWire(ID(my_wire), 1);
+
+		std::string design_str = design.to_rtlil_str();
+
+		EXPECT_NE(design_str.find("module \\my_module"), std::string::npos);
+		EXPECT_NE(design_str.find("end"), std::string::npos);
+	}
+
+	TEST(RtlilStrTest, ModuleToString) {
+		Design design;
+		Module *mod = design.addModule(ID(test_mod));
+		Wire *wire = mod->addWire(ID(clk), 1);
+		wire->port_input = true;
+
+		std::string mod_str = mod->to_rtlil_str();
+
+		EXPECT_NE(mod_str.find("module \\test_mod"), std::string::npos);
+		EXPECT_NE(mod_str.find("wire"), std::string::npos);
+		EXPECT_NE(mod_str.find("\\clk"), std::string::npos);
+		EXPECT_NE(mod_str.find("input"), std::string::npos);
+	}
+
+	TEST(RtlilStrTest, WireToString) {
+		Design design;
+		Module *mod = design.addModule(ID(m));
+		Wire *wire = mod->addWire(ID(data), 8);
+
+		std::string wire_str = wire->to_rtlil_str();
+
+		EXPECT_NE(wire_str.find("wire"), std::string::npos);
+		EXPECT_NE(wire_str.find("width 8"), std::string::npos);
+		EXPECT_NE(wire_str.find("\\data"), std::string::npos);
+	}
+
+	TEST(RtlilStrTest, CellToString) {
+		Design design;
+		Module *mod = design.addModule(ID(m));
+		Cell *cell = mod->addCell(ID(u1), ID(my_cell_type));
+
+		std::string cell_str = cell->to_rtlil_str();
+
+		EXPECT_NE(cell_str.find("cell"), std::string::npos);
+		EXPECT_NE(cell_str.find("\\my_cell_type"), std::string::npos);
+		EXPECT_NE(cell_str.find("\\u1"), std::string::npos);
+	}
+
+}
+
+YOSYS_NAMESPACE_END

tests/unit/opt/optDffFindComplementaryPatternTest.cc

@@ -0,0 +1,179 @@
+#include <gtest/gtest.h>
+#include "kernel/pattern.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+class FindComplementaryPatternVarTest : public ::testing::Test {
+protected:
+	RTLIL::Design *design;
+	RTLIL::Module *module;
+	RTLIL::Wire *wire_a;
+	RTLIL::Wire *wire_b;
+	RTLIL::Wire *wire_c;
+	RTLIL::Wire *bus;
+
+	void SetUp() override {
+		design = new RTLIL::Design;
+		module = design->addModule(ID(test_module));
+		wire_a = module->addWire(ID(a));
+		wire_b = module->addWire(ID(b));
+		wire_c = module->addWire(ID(c));
+		bus = module->addWire(ID(bus), 4);
+	}
+
+	void TearDown() override {
+		delete design;
+	}
+
+	RTLIL::SigBit bit(RTLIL::Wire *w, int offset = 0) {
+		return RTLIL::SigBit(w, offset);
+	}
+};
+
+TEST_F(FindComplementaryPatternVarTest, EmptyPatterns) {
+	pattern_t left, right;
+
+	auto result = find_complementary_pattern_var(left, right);
+	EXPECT_FALSE(result.has_value());
+}
+
+TEST_F(FindComplementaryPatternVarTest, IdenticalSingleVar) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	right[bit(wire_a)] = true;
+
+	auto result = find_complementary_pattern_var(left, right);
+	EXPECT_FALSE(result.has_value());
+}
+
+TEST_F(FindComplementaryPatternVarTest, ComplementarySingleVar) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	right[bit(wire_a)] = false;
+
+	auto result = find_complementary_pattern_var(left, right);
+	ASSERT_TRUE(result.has_value());
+	EXPECT_EQ(result.value(), bit(wire_a));
+}
+
+TEST_F(FindComplementaryPatternVarTest, MissingKeyInRight) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	left[bit(wire_b)] = false;
+	right[bit(wire_a)] = true;
+
+	auto result = find_complementary_pattern_var(left, right);
+	EXPECT_FALSE(result.has_value());
+}
+
+TEST_F(FindComplementaryPatternVarTest, TwoVarsOneComplementary) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	left[bit(wire_b)] = false;
+	right[bit(wire_a)] = true;
+	right[bit(wire_b)] = true;
+
+	auto result = find_complementary_pattern_var(left, right);
+	ASSERT_TRUE(result.has_value());
+	EXPECT_EQ(result.value(), bit(wire_b));
+}
+
+TEST_F(FindComplementaryPatternVarTest, TwoVarsBothComplementary) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	left[bit(wire_b)] = false;
+	right[bit(wire_a)] = false;
+	right[bit(wire_b)] = true;
+
+	auto result = find_complementary_pattern_var(left, right);
+	EXPECT_FALSE(result.has_value());
+}
+
+TEST_F(FindComplementaryPatternVarTest, LeftSubsetOfRight) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	left[bit(wire_b)] = false;
+	right[bit(wire_a)] = true;
+	right[bit(wire_b)] = true;
+	right[bit(wire_c)] = false;
+
+	auto result = find_complementary_pattern_var(left, right);
+	ASSERT_TRUE(result.has_value());
+	EXPECT_EQ(result.value(), bit(wire_b));
+}
+
+TEST_F(FindComplementaryPatternVarTest, ThreeVarsAllSame) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	left[bit(wire_b)] = false;
+	left[bit(wire_c)] = true;
+	right[bit(wire_a)] = true;
+	right[bit(wire_b)] = false;
+	right[bit(wire_c)] = true;
+
+	auto result = find_complementary_pattern_var(left, right);
+	EXPECT_FALSE(result.has_value());
+}
+
+TEST_F(FindComplementaryPatternVarTest, PracticalPatternSimplification) {
+	pattern_t pattern1, pattern2;
+	pattern1[bit(bus, 0)] = true;
+	pattern1[bit(bus, 1)] = true;
+	pattern2[bit(bus, 0)] = true;
+	pattern2[bit(bus, 1)] = false;
+
+	auto result = find_complementary_pattern_var(pattern1, pattern2);
+	ASSERT_TRUE(result.has_value());
+	EXPECT_EQ(result.value(), bit(bus, 1));
+
+	// Swapped args
+	auto result2 = find_complementary_pattern_var(pattern2, pattern1);
+	ASSERT_TRUE(result2.has_value());
+	EXPECT_EQ(result2.value(), bit(bus, 1));
+}
+
+TEST_F(FindComplementaryPatternVarTest, MuxTreeClockEnableDetection) {
+	pattern_t feedback_path1, feedback_path2;
+	feedback_path1[bit(wire_a)] = true;
+	feedback_path1[bit(wire_b)] = true;
+	feedback_path2[bit(wire_a)] = true;
+	feedback_path2[bit(wire_b)] = false;
+
+	auto comp = find_complementary_pattern_var(feedback_path1, feedback_path2);
+	ASSERT_TRUE(comp.has_value());
+	EXPECT_EQ(comp.value(), bit(wire_b));
+
+	pattern_t simplified = feedback_path1;
+	simplified.erase(comp.value());
+
+	EXPECT_EQ(simplified.size(), 1);
+	EXPECT_TRUE(simplified.count(bit(wire_a)));
+	EXPECT_TRUE(simplified[bit(wire_a)]);
+}
+
+TEST_F(FindComplementaryPatternVarTest, AsymmetricPatterns) {
+	pattern_t left, right;
+	left[bit(wire_a)] = true;
+	right[bit(wire_a)] = false;
+	right[bit(wire_b)] = true;
+	right[bit(wire_c)] = false;
+
+	auto result = find_complementary_pattern_var(left, right);
+	ASSERT_TRUE(result.has_value());
+	EXPECT_EQ(result.value(), bit(wire_a));
+}
+
+TEST_F(FindComplementaryPatternVarTest, WireOffsetDistinction) {
+	pattern_t left, right;
+	left[bit(bus, 0)] = true;
+	left[bit(bus, 1)] = false;
+	right[bit(bus, 0)] = true;
+	right[bit(bus, 1)] = true;
+	right[bit(bus, 2)] = false;
+
+	auto result = find_complementary_pattern_var(left, right);
+	ASSERT_TRUE(result.has_value());
+	EXPECT_EQ(result.value(), bit(bus, 1));
+}
+
+YOSYS_NAMESPACE_END

tests/various/debugon.ys

@@ -0,0 +1,14 @@
+# Test debug -on/-off modes
+
+design -reset
+
+read_verilog <<EOT
+module top(input a, input b, output y);
+    assign y = a & b;
+endmodule
+EOT
+
+debug -on
+hierarchy
+select -assert-count 1 t:$and
+debug -off

tests/verific/mixed_flist.flist

@@ -0,0 +1,2 @@
+mixed_flist.sv
+mixed_flist.vhd

tests/verific/mixed_flist.sv

@@ -0,0 +1,4 @@
+module sv_top(input logic a, output logic y);
+	// Instantiates VHDL entity to ensure mixed -f list is required
+	vhdl_mod u_vhdl(.a(a), .y(y));
+endmodule

tests/verific/mixed_flist.vhd

@@ -0,0 +1,14 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_mod is
+	port (
+		a : in std_logic;
+		y : out std_logic
+	);
+end entity vhdl_mod;
+
+architecture rtl of vhdl_mod is
+begin
+	y <= a;
+end architecture rtl;

tests/verific/mixed_flist.ys

@@ -0,0 +1,3 @@
+verific -f -sv mixed_flist.flist
+verific -import sv_top
+select -assert-mod-count 1 sv_top